From patchwork Wed Apr 5 08:01:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 79500 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp140780vqo; Wed, 5 Apr 2023 01:30:01 -0700 (PDT) X-Google-Smtp-Source: AKy350asSixGSc/GU6owgU0dK0AK/E6kvJic0fpZ6Ud1QceVusEEb82xjRbfyKP3d0aKpwFnl0EQ X-Received: by 2002:a17:906:9485:b0:932:e9c7:c32 with SMTP id t5-20020a170906948500b00932e9c70c32mr2280330ejx.59.1680683401118; Wed, 05 Apr 2023 01:30:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680683401; cv=none; d=google.com; s=arc-20160816; b=L3LqyxTAvX49uIr6LJYAK2vuBnr1H2OcjkEVnWvifUmK+YIlNlemiOu/ykfP/X+9nR 2Ru2wieyz4o/oQVfVyyrdQZVHIlf18NR+W+lhtWLQOAoq/WVfaG45lQzJc9ppLZ/Ddsr 8GTA5vZy4sDq1mD58x5fCBjcJrZrCP8diB0B5cj+jq2VHxt62lc30qd2luZcfhCbffWV 3xFf0kz7xr/h1dltoirEX19CtTBm8kFP9UYDQ9O40EfgUZNemeUc8HdisIxYulhOTpUJ J0s2JLoMuNyrrFU7cQCFF73omonSXnDseRI9eqBktw14RbrhsWckgVY10zfi6h2+G+Iq 75sg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=wB+Tm9lKVoh5HUY8IHEflDseB0nA6mqscOZAFXx+cdo=; b=Y10r0WnBaQFDXUnRIljn30f2oGIXYlJoVwK3lv/bH4zXe13yQIFdqzLlmLFnXUauHX MdDhF08CAPTgRgoSkXPX3tP/Fm+3rTKoqJnDCKz6vwu0JPk/ydDdG3WFv9fnuSw0bDuI CTCiOq7GO/Aaac0hXIvjZrPhOJ1T8Rn6PC3Fj3pQ++iR7uEDdXq1e8nlUc46pmDNPkPM Q2cxO51IdVDl9useAWNniKkG9lKOMZaYgVcXAm592SWIhQHTKbrLNqY3XDE+/AUZMAXG WDGCHcfKYrEmp+bU+AToUfqbHVxjm6relbVeg87rYsxrmjw0iLAX1uKPJMX9Z+qumXWf l3tg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=HjvVOzik; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id i20-20020a056402055400b005002ec25762si1212406edx.192.2023.04.05.01.29.37; Wed, 05 Apr 2023 01:30:01 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=HjvVOzik; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237279AbjDEIC2 (ORCPT + 99 others); Wed, 5 Apr 2023 04:02:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237231AbjDEICT (ORCPT ); Wed, 5 Apr 2023 04:02:19 -0400 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 27DD340EE; Wed, 5 Apr 2023 01:02:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1680681738; x=1712217738; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5O3kpADpDKviaqUjctZBRUN1WdPPnVBWYgqfDgkMEqo=; b=HjvVOzik2rrOD23vuSuMIoCVn0t6+UIxHMTKxz6Y9eX7Mrd5Tbe/QuUb 9VnaiBDpgH39FSa4VLP+vH2PDrVAhit36SijPnuBommRBtMou34ErB7Le Y5x/hYAuzSRoSJVegPP0EwrFHam/sEzKBL/vy2oP1or9Iw2cPVqFUYwwp HqXuLcH0xfLFa79Tbf4tgSBFKlqSeEgqOfNZGlqq7Mn7BwabGo+Ta4UlQ U5cIdlBO/qG+unF0JVlWKBERoW0PhKvzsSQ7v9OVVQ4UivpmPCV/g6qMS Sre055REEycQXuF8ePL6OfaKZSHEpLnPeprHzgiCe3iXP+bpNDZc/Bta7 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10670"; a="428680225" X-IronPort-AV: E=Sophos;i="5.98,319,1673942400"; d="scan'208";a="428680225" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Apr 2023 01:02:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10670"; a="775959628" X-IronPort-AV: E=Sophos;i="5.98,319,1673942400"; d="scan'208";a="775959628" Received: from wtedesch-mobl1.ger.corp.intel.com (HELO ijarvine-MOBL2.ger.corp.intel.com) ([10.252.53.134]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Apr 2023 01:02:08 -0700 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: Wu Hao , Tom Rix , Moritz Fischer , Xu Yilun , linux-fpga@vger.kernel.org, Lee Jones , Jean Delvare , Guenter Roeck , linux-hwmon@vger.kernel.org, Russ Weight , linux-kernel@vger.kernel.org Cc: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Subject: [PATCH 2/4] mfd: intel-m10-bmc: Create m10bmc_sys_update_bits() Date: Wed, 5 Apr 2023 11:01:50 +0300 Message-Id: <20230405080152.6732-3-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230405080152.6732-1-ilpo.jarvinen@linux.intel.com> References: <20230405080152.6732-1-ilpo.jarvinen@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.4 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762324278060045694?= X-GMAIL-MSGID: =?utf-8?q?1762324278060045694?= Wrap regmap_update_bits() with m10bmc_sys_update_bits() in order to be able to add additional checks into it. Co-developed-by: Russ Weight Signed-off-by: Russ Weight Signed-off-by: Ilpo Järvinen --- drivers/fpga/intel-m10-bmc-sec-update.c | 30 ++++++++++++------------- drivers/mfd/intel-m10-bmc-core.c | 9 ++++++++ include/linux/mfd/intel-m10-bmc.h | 4 ++++ 3 files changed, 27 insertions(+), 16 deletions(-) diff --git a/drivers/fpga/intel-m10-bmc-sec-update.c b/drivers/fpga/intel-m10-bmc-sec-update.c index d7e2f9f461bc..fe0127a58eff 100644 --- a/drivers/fpga/intel-m10-bmc-sec-update.c +++ b/drivers/fpga/intel-m10-bmc-sec-update.c @@ -376,12 +376,11 @@ static enum fw_upload_err rsu_update_init(struct m10bmc_sec *sec) u32 doorbell_reg, progress, status; int ret, err; - ret = regmap_update_bits(sec->m10bmc->regmap, - csr_map->base + csr_map->doorbell, - DRBL_RSU_REQUEST | DRBL_HOST_STATUS, - DRBL_RSU_REQUEST | - FIELD_PREP(DRBL_HOST_STATUS, - HOST_STATUS_IDLE)); + ret = m10bmc_sys_update_bits(sec->m10bmc, csr_map->doorbell, + DRBL_RSU_REQUEST | DRBL_HOST_STATUS, + DRBL_RSU_REQUEST | + FIELD_PREP(DRBL_HOST_STATUS, + HOST_STATUS_IDLE)); if (ret) return FW_UPLOAD_ERR_RW_ERROR; @@ -450,11 +449,10 @@ static enum fw_upload_err rsu_send_data(struct m10bmc_sec *sec) u32 doorbell_reg, status; int ret; - ret = regmap_update_bits(sec->m10bmc->regmap, - csr_map->base + csr_map->doorbell, - DRBL_HOST_STATUS, - FIELD_PREP(DRBL_HOST_STATUS, - HOST_STATUS_WRITE_DONE)); + ret = m10bmc_sys_update_bits(sec->m10bmc, csr_map->doorbell, + DRBL_HOST_STATUS, + FIELD_PREP(DRBL_HOST_STATUS, + HOST_STATUS_WRITE_DONE)); if (ret) return FW_UPLOAD_ERR_RW_ERROR; @@ -517,11 +515,10 @@ static enum fw_upload_err rsu_cancel(struct m10bmc_sec *sec) if (rsu_prog(doorbell) != RSU_PROG_READY) return FW_UPLOAD_ERR_BUSY; - ret = regmap_update_bits(sec->m10bmc->regmap, - csr_map->base + csr_map->doorbell, - DRBL_HOST_STATUS, - FIELD_PREP(DRBL_HOST_STATUS, - HOST_STATUS_ABORT_RSU)); + ret = m10bmc_sys_update_bits(sec->m10bmc, csr_map->doorbell, + DRBL_HOST_STATUS, + FIELD_PREP(DRBL_HOST_STATUS, + HOST_STATUS_ABORT_RSU)); if (ret) return FW_UPLOAD_ERR_RW_ERROR; @@ -764,3 +761,4 @@ module_platform_driver(intel_m10bmc_sec_driver); MODULE_AUTHOR("Intel Corporation"); MODULE_DESCRIPTION("Intel MAX10 BMC Secure Update"); MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS(INTEL_M10_BMC_CORE); diff --git a/drivers/mfd/intel-m10-bmc-core.c b/drivers/mfd/intel-m10-bmc-core.c index b94412813887..879d98b9b14d 100644 --- a/drivers/mfd/intel-m10-bmc-core.c +++ b/drivers/mfd/intel-m10-bmc-core.c @@ -12,6 +12,15 @@ #include #include +int m10bmc_sys_update_bits(struct intel_m10bmc *m10bmc, unsigned int offset, + unsigned int msk, unsigned int val) +{ + const struct m10bmc_csr_map *csr_map = m10bmc->info->csr_map; + + return regmap_update_bits(m10bmc->regmap, csr_map->base + offset, msk, val); +} +EXPORT_SYMBOL_NS_GPL(m10bmc_sys_update_bits, INTEL_M10_BMC_CORE); + static ssize_t bmc_version_show(struct device *dev, struct device_attribute *attr, char *buf) { diff --git a/include/linux/mfd/intel-m10-bmc.h b/include/linux/mfd/intel-m10-bmc.h index 1812ebfa11a8..5418f7279ed0 100644 --- a/include/linux/mfd/intel-m10-bmc.h +++ b/include/linux/mfd/intel-m10-bmc.h @@ -251,6 +251,7 @@ struct intel_m10bmc { * * m10bmc_raw_read - read m10bmc register per addr * m10bmc_sys_read - read m10bmc system register per offset + * m10bmc_sys_update_bits - update m10bmc system register per offset */ static inline int m10bmc_raw_read(struct intel_m10bmc *m10bmc, unsigned int addr, @@ -282,6 +283,9 @@ static inline int m10bmc_sys_read(struct intel_m10bmc *m10bmc, unsigned int offs return m10bmc_raw_read(m10bmc, csr_map->base + offset, val); } +int m10bmc_sys_update_bits(struct intel_m10bmc *m10bmc, unsigned int offset, + unsigned int msk, unsigned int val); + /* * MAX10 BMC Core support */