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From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
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Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Subject: [PATCH 5/5] arm64: dts: qcom: sm8450: simplify interrupts-extended
Date: Wed, 5 Apr 2023 08:09:06 +0200
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| Series |
[1/5] arm64: dts: qcom: sc8280xp: label the Soundwire nodes
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Commit Message
Krzysztof Kozlowski
April 5, 2023, 6:09 a.m. UTC
The parent controller for both interrupts is GIC, so no need for
interrupts-extended.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Comments
On 5.04.2023 08:09, Krzysztof Kozlowski wrote: > The parent controller for both interrupts is GIC, so no need for > interrupts-extended. > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > arch/arm64/boot/dts/qcom/sm8450.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index 1dd000748f9e..1dc5d2c49aad 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -2298,8 +2298,8 @@ swr0: soundwire-controller@3250000 { > swr2: soundwire-controller@33b0000 { > compatible = "qcom,soundwire-v1.7.0"; > reg = <0 0x033b0000 0 0x2000>; > - interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, > - <&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; > + interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; > interrupt-names = "core", "wakeup"; > > clocks = <&vamacro>;
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 1dd000748f9e..1dc5d2c49aad 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2298,8 +2298,8 @@ swr0: soundwire-controller@3250000 { swr2: soundwire-controller@33b0000 { compatible = "qcom,soundwire-v1.7.0"; reg = <0 0x033b0000 0 0x2000>; - interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "core", "wakeup"; clocks = <&vamacro>;