From patchwork Tue Apr 4 10:47:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 78988 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2927837vqo; Tue, 4 Apr 2023 03:49:37 -0700 (PDT) X-Google-Smtp-Source: AKy350ZO8/vhtnyGzOzqfgG0/dIdDPBJB0Edyen07PMhYGZcNPkjySbgqcsfvUawXoE2egQR7nwA X-Received: by 2002:a17:906:9c8a:b0:948:d1af:3a11 with SMTP id fj10-20020a1709069c8a00b00948d1af3a11mr1779241ejc.50.1680605377724; Tue, 04 Apr 2023 03:49:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680605377; cv=none; d=google.com; s=arc-20160816; b=HNlLiR6ri6OcuWUdmLRV0sHSJAMVyNpUrlgfKLoyYleqkfkIm4Ly7lv3cSk9EGBbL0 s79IE9SxiW8S3UsZPdC5m4sjEoAcXH5n4ZgMIECy2NEifIK01WXKReGLxgI0XjxZZ7yk UNOaThrcUX7JMzPO8lajZ9DM86Vw+k+QmU399iLvmVwLq3fc2K7Ay3gmoUV+syInGPkG 5XLKzhkT8HGuAg5QpKWVvXXAIuqRPSkEtzW5f2+pLhAjiZPcendapoRXs6oSoZncn81m xUiKv0CDJA9ZWRboBp1+8lVu/AeYkcahR0QpSmItRum/IzagD4TLaeTbehBV5E40hqGm G70g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=J5DWD32OWLq13uaRlJE+1ppOi8qnCqTf5ZEGPUBOy/k=; b=uVq1KEzVr7RQx5XlvCzVNa/DBR8y1exablmZygEdtN6WvldxAtg55pxAh1R9N1uXIL Am7WvqJ8YFqbcJg5skN+kLz5BT/0afIKCzdN9zCdgWePFhNfQ7NCfxMRPELffbj3ql/B SKj8RwO+iBsUS5mhAMWt+/drjan/R9zbpHWLwWnf2rMQ1dVdUF2RmlTXVxdJiW2807yy Vd/wVAPJ8qwTVlU9z9noPetF73irctQn+qfaPHgcygMWoMFioBajugGGsZDBuTRThOfU EfDzgKWCuhpGhEU1qe/suo45yso310BTYJXXQAyjfWiboY81ZSd5AM3Vo987oxdSi3Fg DIdw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=ETl2LZ5B; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id z18-20020a170906271200b0092be82bf914si811650ejc.863.2023.04.04.03.49.13; Tue, 04 Apr 2023 03:49:37 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=ETl2LZ5B; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234570AbjDDKsX (ORCPT + 99 others); Tue, 4 Apr 2023 06:48:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57102 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234538AbjDDKsL (ORCPT ); Tue, 4 Apr 2023 06:48:11 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7E4F91737 for ; Tue, 4 Apr 2023 03:48:09 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id F1C1F66031A6; Tue, 4 Apr 2023 11:48:06 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1680605287; bh=IS0da1vr/9JtA9BZ0bqYXl4kxrPBhntX0yK9vYbXQe0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ETl2LZ5B0dPCEdKCCHFJa7r9nE7hqf3FX9QX+Ef2UPuNT0deDxMYBJ8jhGINo6Iwm OF8RLZ5vxvBJU1JpBbb4m0RdkjZuMMIIji9O6zQH3zesvhvDqK8sztiQ4gdEy4K8g2 dI8ge8h3/H2+IPAmfHjOZXYxK/FeMjXQgxPt64ArwcqXgft1sacwP/jfHeSX0esh5S OdCvC2CCe/uFTRV/CMI+2yu/qrf97Yacvn3aXmvJqG/EjDon5HYu2wr2sFjeuzcPgl coNYcYEUqo/huY6Kz0fCl52jpaqz43qcjhdC1Ji8GRwj3GqB3Xp5U06rwS/MTmetVX Ere/RQ3GrkvQg== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v3 2/9] drm/mediatek: dp: Move AUX and panel poweron/off sequence to function Date: Tue, 4 Apr 2023 12:47:53 +0200 Message-Id: <20230404104800.301150-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230404104800.301150-1-angelogioacchino.delregno@collabora.com> References: <20230404104800.301150-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762242464563371217?= X-GMAIL-MSGID: =?utf-8?q?1762242464563371217?= Everytime we run bridge detection and/or EDID read we run a poweron and poweroff sequence for both the AUX and the panel; moreover, this is also done when enabling the bridge in the .atomic_enable() callback. Move this power on/off sequence to a new mtk_dp_aux_panel_poweron() function as to commonize it. Note that, before this commit, in mtk_dp_bridge_atomic_enable() only the AUX was getting powered on but the panel was left powered off if the DP cable wasn't plugged in while now we unconditionally send a D0 request and this is done for two reasons: - First, whether this request fails or not, it takes the same time and anyway the DP hardware won't produce any error (or, if it does, it's ignorable because it won't block further commands) - Second, training the link between a sleeping/standby/unpowered display makes little sense. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_dp.c | 76 ++++++++++++------------------- 1 file changed, 30 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c index 84f82cc68672..76ea94167531 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp.c +++ b/drivers/gpu/drm/mediatek/mtk_dp.c @@ -1253,6 +1253,29 @@ static void mtk_dp_audio_mute(struct mtk_dp *mtk_dp, bool mute) val[2], AU_TS_CFG_DP_ENC0_P0_MASK); } +static void mtk_dp_aux_panel_poweron(struct mtk_dp *mtk_dp, bool pwron) +{ + if (pwron) { + /* power on aux */ + mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, + DP_PWR_STATE_BANDGAP_TPLL_LANE, + DP_PWR_STATE_MASK); + + /* power on panel */ + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); + usleep_range(2000, 5000); + } else { + /* power off panel */ + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D3); + usleep_range(2000, 3000); + + /* power off aux */ + mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, + DP_PWR_STATE_BANDGAP_TPLL, + DP_PWR_STATE_MASK); + } +} + static void mtk_dp_power_enable(struct mtk_dp *mtk_dp) { mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_RESET_AND_PROBE, @@ -1937,16 +1960,9 @@ static enum drm_connector_status mtk_dp_bdg_detect(struct drm_bridge *bridge) if (!mtk_dp->train_info.cable_plugged_in) return ret; - if (!enabled) { - /* power on aux */ - mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, - DP_PWR_STATE_BANDGAP_TPLL_LANE, - DP_PWR_STATE_MASK); + if (!enabled) + mtk_dp_aux_panel_poweron(mtk_dp, true); - /* power on panel */ - drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); - usleep_range(2000, 5000); - } /* * Some dongles still source HPD when they do not connect to any * sink device. To avoid this, we need to read the sink count @@ -1958,16 +1974,8 @@ static enum drm_connector_status mtk_dp_bdg_detect(struct drm_bridge *bridge) if (DP_GET_SINK_COUNT(sink_count)) ret = connector_status_connected; - if (!enabled) { - /* power off panel */ - drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D3); - usleep_range(2000, 3000); - - /* power off aux */ - mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, - DP_PWR_STATE_BANDGAP_TPLL, - DP_PWR_STATE_MASK); - } + if (!enabled) + mtk_dp_aux_panel_poweron(mtk_dp, false); return ret; } @@ -1983,15 +1991,7 @@ static struct edid *mtk_dp_get_edid(struct drm_bridge *bridge, if (!enabled) { drm_atomic_bridge_chain_pre_enable(bridge, connector->state->state); - - /* power on aux */ - mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, - DP_PWR_STATE_BANDGAP_TPLL_LANE, - DP_PWR_STATE_MASK); - - /* power on panel */ - drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); - usleep_range(2000, 5000); + mtk_dp_aux_panel_poweron(mtk_dp, true); } /* eDP panels aren't removable, so we can return a cached EDID. */ @@ -2015,15 +2015,7 @@ static struct edid *mtk_dp_get_edid(struct drm_bridge *bridge, } if (!enabled) { - /* power off panel */ - drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D3); - usleep_range(2000, 3000); - - /* power off aux */ - mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, - DP_PWR_STATE_BANDGAP_TPLL, - DP_PWR_STATE_MASK); - + mtk_dp_aux_panel_poweron(mtk_dp, false); drm_atomic_bridge_chain_post_disable(bridge, connector->state->state); } @@ -2188,15 +2180,7 @@ static void mtk_dp_bridge_atomic_enable(struct drm_bridge *bridge, return; } - /* power on aux */ - mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, - DP_PWR_STATE_BANDGAP_TPLL_LANE, - DP_PWR_STATE_MASK); - - if (mtk_dp->train_info.cable_plugged_in) { - drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); - usleep_range(2000, 5000); - } + mtk_dp_aux_panel_poweron(mtk_dp, true); /* Training */ ret = mtk_dp_training(mtk_dp);