From patchwork Tue Apr 4 10:26:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 79022 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2952950vqo; Tue, 4 Apr 2023 04:33:58 -0700 (PDT) X-Google-Smtp-Source: AKy350Yi7Bw32KKb3wZ0/3nyVSHHRjms3qEd9B2LJ/TyuhznLWh3okNVfO/8Z9/WMF2LWMYtZdV1 X-Received: by 2002:a17:906:3a93:b0:933:9f43:5c3b with SMTP id y19-20020a1709063a9300b009339f435c3bmr1981444ejd.59.1680608037916; Tue, 04 Apr 2023 04:33:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680608037; cv=none; d=google.com; s=arc-20160816; b=eV7pIVsoYkVrV0YxHW1a+BtPPWildXZ7RMWU8NYJIqnpeZG8U6UJZuI9URxLoI1OZG Bd/93Daql2lc0pq7998D72ddkOWgXoeabA9zDePujBtySvYxtxcXoWrsW7G7dMCy5epc EXixF83A0gfm+Ek0SK9yqk0AitYdsqN+nhoPHHuXBUnmQqmlTs5GX+lg1i+BTWbKnymB IC6mGKWR5tRcFv2tx5Jy4X6qnFTHHA8ajAJ6X16hJFMHlE1eXdihpH2lCQd/V2iTyogT MqxGAn98S7tCKCRU9/YA6KhQ01XKaWb/BqPKWG2cF152mG/iGySW83g6Kj9+CAA8bLbR YDaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=s1TnurdU9eI1YRCwil5WMrFTmYZQx9ZLxqgiOpLcQhQ=; b=0yDBdrvab3Y7mPzILJu8iOE7t84bZmOEDBEqG2SXqdEkt7vhjAWyNKkuu3d46AQN43 egvzuN7HPjnrcJOAplbiJE2c5aOlU61S3nbUQiDdTV2JSD7Fkw8YhvOKxDUbvmoYsGeM 1gjHCIYMAkz2q6YA7cbOWvuzbP3jqPB65GXboe6sObw3nfYu9aCR+/+ejMAknEZj7GRh a00aqmPnidinSuDeO0FZRzIncNgihgjNf9BbJicAb/f9nm6cJxsjoY+ZL2O1kOh0rcbh Usp4VW6pZGGNDZ87AoSOty3ojoVyerndeQzIcROvTxJ3QA6bJiYr27aoGWwFEIFmncd7 lpQw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="PzWQ/BE2"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id p11-20020a170906b20b00b0093defbd6296si322523ejz.1053.2023.04.04.04.33.33; Tue, 04 Apr 2023 04:33:57 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="PzWQ/BE2"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234814AbjDDKyV (ORCPT + 99 others); Tue, 4 Apr 2023 06:54:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40208 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234692AbjDDKx1 (ORCPT ); Tue, 4 Apr 2023 06:53:27 -0400 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A91253C3F; Tue, 4 Apr 2023 03:53:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1680605586; x=1712141586; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=g68cyMdX2debPTjgjq16HL+D6AhwC/hj42OGPtnTvek=; b=PzWQ/BE2BbeIhoYfuyfjKc46RonsVONG14WtYF9M+R0wAtCtXq80VwxR WQiEeHMt5xikMSLwJ4dLfaut+IVfRjOfDVwjkfeI2nexQv6VVvXxFDHvU swy8gbqb4x7pf2fgsIoY0gzfLIpAnVBebpzCmVtcahM7bV7TnX1RYFxwe tUYrz+iQcv3eCTnPUKWCQuZ5G7Z+el9t7WvE37yiyOCnFpRzPOl4hIbb6 wtiLIduzDSeukVxrHFBz9R5UkYFaXtHnUTYDEOMRbMDPlyrwToA3GLEGy j9Avs4TxSyTN7dHlepBwgsQEvj6moehZFRYzGw6wnbHMPCNGYoPUigLSD g==; X-IronPort-AV: E=McAfee;i="6600,9927,10669"; a="330733986" X-IronPort-AV: E=Sophos;i="5.98,317,1673942400"; d="scan'208";a="330733986" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Apr 2023 03:53:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10669"; a="775597795" X-IronPort-AV: E=Sophos;i="5.98,317,1673942400"; d="scan'208";a="775597795" Received: from unknown (HELO fred..) ([172.25.112.68]) by FMSMGA003.fm.intel.com with ESMTP; 04 Apr 2023 03:53:01 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v7 06/33] x86/cpufeature: add the cpu feature bit for FRED Date: Tue, 4 Apr 2023 03:26:49 -0700 Message-Id: <20230404102716.1795-7-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404102716.1795-1-xin3.li@intel.com> References: <20230404102716.1795-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762245253991322106?= X-GMAIL-MSGID: =?utf-8?q?1762245253991322106?= From: "H. Peter Anvin (Intel)" Add the CPU feature bit for FRED (Flexible Return and Event Delivery). The Intel flexible return and event delivery (FRED) architecture defines simple new transitions that change privilege level (ring transitions). The FRED architecture was designed with the following goals: 1) Improve overall performance and response time by replacing event delivery through the interrupt descriptor table (IDT event delivery) and event return by the IRET instruction with lower latency transitions. 2) Improve software robustness by ensuring that event delivery establishes the full supervisor context and that event return establishes the full user context. The new transitions defined by the FRED architecture are FRED event delivery and, for returning from events, two FRED return instructions. FRED event delivery can effect a transition from ring 3 to ring 0, but it is used also to deliver events incident to ring 0. One FRED instruction (ERETU) effects a return from ring 0 to ring 3, while the other (ERETS) returns while remaining in ring 0. Search for the latest FRED spec in most search engines with this search pattern: site:intel.com FRED (flexible return and event delivery) specification Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/asm/cpufeatures.h | 1 + tools/arch/x86/include/asm/cpufeatures.h | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 73c9672c123b..1fa444478d33 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -318,6 +318,7 @@ #define X86_FEATURE_FZRM (12*32+10) /* "" Fast zero-length REP MOVSB */ #define X86_FEATURE_FSRS (12*32+11) /* "" Fast short REP STOSB */ #define X86_FEATURE_FSRC (12*32+12) /* "" Fast short REP {CMPSB,SCASB} */ +#define X86_FEATURE_FRED (12*32+17) /* Flexible Return and Event Delivery */ #define X86_FEATURE_LKGS (12*32+18) /* "" Load "kernel" (userspace) GS */ #define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */ #define X86_FEATURE_AVX_IFMA (12*32+23) /* "" Support for VPMADD52[H,L]UQ */ diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h index b89005819cd5..e9064f4a011a 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -312,6 +312,7 @@ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */ #define X86_FEATURE_CMPCCXADD (12*32+ 7) /* "" CMPccXADD instructions */ +#define X86_FEATURE_FRED (12*32+17) /* Flexible Return and Event Delivery */ #define X86_FEATURE_LKGS (12*32+18) /* "" Load "kernel" (userspace) GS */ #define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */ #define X86_FEATURE_AVX_IFMA (12*32+23) /* "" Support for VPMADD52[H,L]UQ */