From patchwork Mon Apr 3 17:36:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 78655 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2475607vqo; Mon, 3 Apr 2023 10:45:06 -0700 (PDT) X-Google-Smtp-Source: AKy350ZDxYWjCkUcII0zT+SkBxDLuxg+YMfFQuETIKuHwYrRubufTwQP+bwGyYegYZ00MgjfV6Jm X-Received: by 2002:a05:6a20:3544:b0:e3:6feb:fb6a with SMTP id f4-20020a056a20354400b000e36febfb6amr16441501pze.40.1680543905969; Mon, 03 Apr 2023 10:45:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680543905; cv=none; d=google.com; s=arc-20160816; b=NdSsKJHpM3afzURJnD1R1DnGn54UVNceX393gqfgrBOo9ds4AYf3IsncWHd5dR5FHa el6ZDnJjA44BFb/LiZjdYfuCF6ik7onOgF8vDhAa2wby82/F+JIOb9ex3eA1V77WislF JsLQygHT0inp1Gfi46irPDJnExmEumadlBFnYapzWEJSULZu1Evs29IEW5OOZkKJz9yx N4sESioYKBurLpvcdRhW42GS9+g3STlkImQ8FiHReIGz4mHh2BHCqM0WGRSlXfYRw3Wy qwnCOiXXVTsDpt75v3wWYwIy+J7Y9rNT+EJCUPEibAC7FK+QcM2lv4wdEmx9z6JJXkRU SeaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=YDSUqIgZc3vuE7G0wttUjC5sMF8eoKNUAXbG/+xBz7o=; b=ZPFxHqYtM+4I7PvpnQAaShaqyMZkDc59+fi0dhIoSXmTndP9yNYBdWDNBvlGDPSiM4 xjm7TPDcvVsh9OJQuoG1uLC3+hCbrROWbeUrsCSodS8gAQPRFBLUA0kNiiOHpwsM0SqD H7UW3R4mwRiF7dVQ9ibydRM6V4kYQv/VFDwE696p3oawIZj+DLbimvvQGjmpqL0VHpkH /l19SPthlXjpA5czeQEG8vA2uvAuUhHNIdAOMxbCbkJuebv5C8AQO5oytWrgpkdjk8oj L54YCUHnauNgVk9P4bBAUceQHbaYDaYU7N2S1TvKlEg0LZm8c/dpPKIdbXcrKQPWXQYs AJJA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dfpkob28; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id w5-20020a626205000000b0062dbc05a323si3592461pfb.298.2023.04.03.10.44.52; Mon, 03 Apr 2023 10:45:05 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dfpkob28; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231965AbjDCRgr (ORCPT + 99 others); Mon, 3 Apr 2023 13:36:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39438 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231583AbjDCRge (ORCPT ); Mon, 3 Apr 2023 13:36:34 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2851F30DD for ; Mon, 3 Apr 2023 10:36:32 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id x17so39121731lfu.5 for ; Mon, 03 Apr 2023 10:36:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680543391; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=YDSUqIgZc3vuE7G0wttUjC5sMF8eoKNUAXbG/+xBz7o=; b=dfpkob28ehCs6mCLIcs+gUCzOibZPsfuW0jltZQVgvqUH/lABj46t7tQ4ubT00RNqC Cs59c4z2mY5qbcBCGcdfOzp6wg94StRJz/kwJrSmywv+xGXj97FoQG59187+Wy2Hy9E1 qNf5gLVkKpcUFOWZ0skJ/nr2sJImRZDpZV40wrIZuK8GZ6upwsblJ3TOomBjooLe8DgV SI9v4Nycp4C31UuuXtxZVq7avXTKdH00/lyUqvCkO+JawxHGLcpFaH5OKtWwYyzfjtsy bFvimXy642cIuranElFVXpKgdKBnmcfMyxkHQlgKczJR0PMENye3QUHt9z8uIl5n3D3B tYQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680543391; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YDSUqIgZc3vuE7G0wttUjC5sMF8eoKNUAXbG/+xBz7o=; b=O1afES43GIicbxSU6nEH8bKBuwbxW4nKNkRC6/6QT4XHNuJdtarSOpNOcJjIbmtfow F+K5gZbh7LZEErubA7Kqm7/7pU2EXOAfqVVwyPWPYsfnF/SE5p7V8Qyt3qEaQXJJn+ze zIxhtfooG9g+tIRWosfCn+bM5huyFAfsYC77HNfaSvQRLGXnoRwQ34Sr8sz1+FJEuK+J AB4lrwChaV8DyrC5FAqFpP4Cn/3rzxDz0y5mJIEyvxHXsQh+ceOxCukscvZmqknZoWHQ IOwnbm4eHdTGHsVICJZCKC+WjmsUqyUKIUleM3zg8aK68CaOMxSeNLekThFBnzW7feIZ bx6Q== X-Gm-Message-State: AAQBX9cWxMBKadlTGKkCoWHq81XSVgiAlvmCO8A4U8n45kuPYsxZH1ZW san+Jvw5N5mRa2fYySE3oZyCig== X-Received: by 2002:ac2:46fb:0:b0:4eb:20f:99ee with SMTP id q27-20020ac246fb000000b004eb020f99eemr11378912lfo.63.1680543391499; Mon, 03 Apr 2023 10:36:31 -0700 (PDT) Received: from [192.168.1.101] (abxj135.neoplus.adsl.tpnet.pl. [83.9.3.135]) by smtp.gmail.com with ESMTPSA id v2-20020a056512096200b004cc5f44747dsm1871094lft.220.2023.04.03.10.36.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Apr 2023 10:36:31 -0700 (PDT) From: Konrad Dybcio Date: Mon, 03 Apr 2023 19:36:02 +0200 Subject: [PATCH 4/9] arm64: dts: qcom: qcm2290: Add most QUPs MIME-Version: 1.0 Message-Id: <20230403-topic-rb1_qcm-v1-4-ca849b62ba07@linaro.org> References: <20230403-topic-rb1_qcm-v1-0-ca849b62ba07@linaro.org> In-Reply-To: <20230403-topic-rb1_qcm-v1-0-ca849b62ba07@linaro.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Robert Marko , Das Srinagesh Cc: Bhupesh Sharma , Vladimir Zapolskiy , Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680543384; l=9924; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=h7DNqy7zdnStNn/U/kT1rG4OFD58lx5f9HKEurJdSgg=; b=HU+/8bML8aHHs2aPAEF2zaGH2jMAMzXTreqe8YRJrsMTJjHv2hTqysMh2xyBtV2SCICl1mxQvKNw lLTC1M5wD5KC0SNLR6Dl8T0mTWLkD3nXExVlnDYp3D0Hi8GjlID2 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762178006936160320?= X-GMAIL-MSGID: =?utf-8?q?1762178006936160320?= Add all I2C and SPI hosts, the debug UART port and the related pinctrl. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 294 ++++++++++++++++++++++++++++++++++ 1 file changed, 294 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index 27d4742cdb19..edfa18190454 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -310,6 +310,90 @@ tlmm: pinctrl@500000 { interrupt-controller; #interrupt-cells = <2>; + qup_i2c0_default: qup-i2c0-default-state { + pins = "gpio0", "gpio1"; + function = "qup0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c1_default: qup-i2c1-default-state { + pins = "gpio4", "gpio5"; + function = "qup1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_default: qup-i2c2-default-state { + pins = "gpio6", "gpio7"; + function = "qup2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c3_default: qup-i2c3-default-state { + pins = "gpio8", "gpio9"; + function = "qup3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c4_default: qup-i2c4-default-state { + pins = "gpio12", "gpio13"; + function = "qup4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c5_default: qup-i2c5-default-state { + pins = "gpio14", "gpio15"; + function = "qup5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi0_default: qup-spi0-default-state { + pins = "gpio0", "gpio1","gpio2", "gpio3"; + function = "qup0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi1_default: qup-spi1-default-state { + pins = "gpio4", "gpio5", "gpio69", "gpio70"; + function = "qup1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi2_default: qup-spi2-default-state { + pins = "gpio6", "gpio7", "gpio71", "gpio80"; + function = "qup2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi3_default: qup-spi3-default-state { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "qup3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi4_default: qup-spi4-default-state { + pins = "gpio12", "gpio13", "gpio96", "gpio97"; + function = "qup4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi5_default: qup-spi5-default-state { + pins = "gpio14", "gpio15", "gpio16", "gpio17"; + function = "qup5"; + drive-strength = <2>; + bias-pull-up; + }; + qup_uart0_default: qup-uart0-default-state { pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "qup0"; @@ -317,6 +401,13 @@ qup_uart0_default: qup-uart0-default-state { bias-disable; }; + qup_uart4_default: qup-uart4-default-state { + pins = "gpio12", "gpio13"; + function = "qup4"; + drive-strength = <2>; + bias-disable; + }; + sdc1_state_on: sdc1-on-state { clk-pins { pins = "sdc1_clk"; @@ -604,6 +695,38 @@ qupv3_id_0: geniqup@4ac0000 { ranges; status = "disabled"; + i2c0: i2c@4a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a80000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c0_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@4a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a80000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi0_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + uart0: serial@4a80000 { compatible = "qcom,geni-uart"; reg = <0x0 0x04a80000 0x0 0x4000>; @@ -614,6 +737,177 @@ uart0: serial@4a80000 { pinctrl-names = "default"; status = "disabled"; }; + + i2c1: i2c@4a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a84000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c1_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@4a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a84000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi1_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@4a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a88000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c2_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@4a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a88000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi2_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@4a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a8c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c3_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@4a8c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a8c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi3_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@4a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a90000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c4_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@4a90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a90000 0x0 0x4000>; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi4_default>; + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart4: serial@4a90000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a90000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart4_default>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c5: i2c@4a94000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a94000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c5_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@4a94000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a94000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi5_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; usb: usb@4ef8800 {