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(fttx-pool-217.61.149.201.bambit.de [217.61.149.201]) by mxbox1.masterlogin.de (Postfix) with ESMTPSA id 8262B4092B; Sun, 2 Apr 2023 13:12:01 +0000 (UTC) From: Frank Wunderlich To: linux-mediatek@lists.infradead.org Cc: Frank Wunderlich , Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Matthias Brugger , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH] PCI: mediatek-gen3: handle PERST after reset Date: Sun, 2 Apr 2023 15:11:19 +0200 Message-Id: <20230402131119.98805-1-linux@fw-web.de> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Mail-ID: 8b6dfb75-3da6-40a2-b803-4599ce6843ed X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762072516986480851?= X-GMAIL-MSGID: =?utf-8?q?1762072843391349492?= From: Frank Wunderlich De-assert PERST in separate step after reset signals to fully comply the PCIe CEM clause 2.2. This fixes some NVME detection issues on mt7986. Fixes: d3bf75b579b9 ("PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192") Signed-off-by: Frank Wunderlich --- Patch is taken from user Ruslan aka RRKh61 (permitted me to send it with me as author). https://forum.banana-pi.org/t/bpi-r3-nvme-connection-issue/14563/17 --- drivers/pci/controller/pcie-mediatek-gen3.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index b8612ce5f4d0..176b1a04565d 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -350,7 +350,13 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie) msleep(100); /* De-assert reset signals */ - val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB); + val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB); + writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); + + msleep(100); + + /* De-assert PERST# signals */ + val &= ~(PCIE_PE_RSTB); writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); /* Check if the link is up or not */