diff mbox series

[v7,22/22] riscv: dts: starfive: jh7110: Correct the properties of S7 core

Message ID 20230401111934.130844-23-hal.feng@starfivetech.com
State New
Headers
Series Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC |

Commit Message

Hal Feng April 1, 2023, 11:19 a.m. UTC 
  The S7 core has no L1 data cache and MMU, so delete some
related properties.

Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 ---------
 1 file changed, 9 deletions(-)
diff mbox series

Patch

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index d484ecdf93f7..4c5fdb905da8 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -20,21 +20,12 @@  cpus {
 		S7_0: cpu@0 {
 			compatible = "sifive,s7", "riscv";
 			reg = <0>;
-			d-cache-block-size = <64>;
-			d-cache-sets = <64>;
-			d-cache-size = <8192>;
-			d-tlb-sets = <1>;
-			d-tlb-size = <40>;
 			device_type = "cpu";
 			i-cache-block-size = <64>;
 			i-cache-sets = <64>;
 			i-cache-size = <16384>;
-			i-tlb-sets = <1>;
-			i-tlb-size = <40>;
-			mmu-type = "riscv,sv39";
 			next-level-cache = <&ccache>;
 			riscv,isa = "rv64imac_zba_zbb";
-			tlb-split;
 			status = "disabled";
 
 			cpu0_intc: interrupt-controller {