Message ID | 20230331105546.13607-17-victor.shih@genesyslogic.com.tw |
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State | New |
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[2001:b400:e25c:983f:c7ff:3efd:77d9:6c16]) by smtp.gmail.com with ESMTPSA id f19-20020a170902e99300b0019acd3151d0sm1287665plb.114.2023.03.31.03.56.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Mar 2023 03:56:48 -0700 (PDT) From: Victor Shih <victorshihgli@gmail.com> X-Google-Original-From: Victor Shih <victor.shih@genesyslogic.com.tw> To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih <victor.shih@genesyslogic.com.tw>, Ben Chuang <ben.chuang@genesyslogic.com.tw> Subject: [PATCH V7 16/23] mmc: sdhci-uhs2: add clock operations Date: Fri, 31 Mar 2023 18:55:39 +0800 Message-Id: <20230331105546.13607-17-victor.shih@genesyslogic.com.tw> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230331105546.13607-1-victor.shih@genesyslogic.com.tw> References: <20230331105546.13607-1-victor.shih@genesyslogic.com.tw> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761881406932550009?= X-GMAIL-MSGID: =?utf-8?q?1761881406932550009?= |
Series |
Add support UHS-II for GL9755
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Commit Message
Victor Shih
March 31, 2023, 10:55 a.m. UTC
This is a sdhci version of mmc's uhs2_[enable|disable]_clk operations. Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw> --- drivers/mmc/host/sdhci-uhs2.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+)
Comments
On 31/03/23 13:55, Victor Shih wrote: > This is a sdhci version of mmc's uhs2_[enable|disable]_clk operations. > > Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> > Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> > Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw> > --- > drivers/mmc/host/sdhci-uhs2.c | 32 ++++++++++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c > index e2972be1889f..71ac76065886 100644 > --- a/drivers/mmc/host/sdhci-uhs2.c > +++ b/drivers/mmc/host/sdhci-uhs2.c > @@ -14,6 +14,7 @@ > #include <linux/module.h> > #include <linux/iopoll.h> > #include <linux/bitfield.h> > +#include <linux/ktime.h> There is no ktime in this patch > > #include "sdhci.h" > #include "sdhci-uhs2.h" > @@ -328,6 +329,37 @@ static int sdhci_uhs2_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) > return 0; > } > > +static int sdhci_uhs2_disable_clk(struct mmc_host *mmc) > +{ > + struct sdhci_host *host = mmc_priv(mmc); > + u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); > + > + clk &= ~SDHCI_CLOCK_CARD_EN; > + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); > + > + return 0; > +} > + > +static int sdhci_uhs2_enable_clk(struct mmc_host *mmc) > +{ > + struct sdhci_host *host = mmc_priv(mmc); > + u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); > + u32 val; > + /* 20ms */ > + int timeout_us = 20000; Let's put the comment on the end and put the lines in descending line length i.e. int timeout_us = 20000; /* 20ms */ u32 val; > + > + clk |= SDHCI_CLOCK_CARD_EN; > + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); > + > + if (read_poll_timeout_atomic(sdhci_readw, val, (val & SDHCI_CLOCK_INT_STABLE), > + 10, timeout_us, true, host, SDHCI_CLOCK_CONTROL)) { atomic does not seem to be needed here > + pr_err("%s: Internal clock never stabilised.\n", mmc_hostname(host->mmc)); > + sdhci_dumpregs(host); > + return 1; return -EIO; > + } > + return 0; > +} > + > /*****************************************************************************\ > * * > * Driver init/exit *
Hi, Adrian On Wed, Apr 12, 2023 at 9:13 PM Adrian Hunter <adrian.hunter@intel.com> wrote: > > On 31/03/23 13:55, Victor Shih wrote: > > This is a sdhci version of mmc's uhs2_[enable|disable]_clk operations. > > > > Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> > > Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> > > Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw> > > --- > > drivers/mmc/host/sdhci-uhs2.c | 32 ++++++++++++++++++++++++++++++++ > > 1 file changed, 32 insertions(+) > > > > diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c > > index e2972be1889f..71ac76065886 100644 > > --- a/drivers/mmc/host/sdhci-uhs2.c > > +++ b/drivers/mmc/host/sdhci-uhs2.c > > @@ -14,6 +14,7 @@ > > #include <linux/module.h> > > #include <linux/iopoll.h> > > #include <linux/bitfield.h> > > +#include <linux/ktime.h> > > There is no ktime in this patch > I will update it to the V8 version. > > > > #include "sdhci.h" > > #include "sdhci-uhs2.h" > > @@ -328,6 +329,37 @@ static int sdhci_uhs2_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) > > return 0; > > } > > > > +static int sdhci_uhs2_disable_clk(struct mmc_host *mmc) > > +{ > > + struct sdhci_host *host = mmc_priv(mmc); > > + u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); > > + > > + clk &= ~SDHCI_CLOCK_CARD_EN; > > + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); > > + > > + return 0; > > +} > > + > > +static int sdhci_uhs2_enable_clk(struct mmc_host *mmc) > > +{ > > + struct sdhci_host *host = mmc_priv(mmc); > > + u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); > > + u32 val; > > + /* 20ms */ > > + int timeout_us = 20000; > > Let's put the comment on the end and put the lines in > descending line length i.e. > > int timeout_us = 20000; /* 20ms */ > u32 val; > I will update it to the V8 version. > > + > > + clk |= SDHCI_CLOCK_CARD_EN; > > + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); > > + > > + if (read_poll_timeout_atomic(sdhci_readw, val, (val & SDHCI_CLOCK_INT_STABLE), > > + 10, timeout_us, true, host, SDHCI_CLOCK_CONTROL)) { > > atomic does not seem to be needed here > I will update it to the V8 version. > > + pr_err("%s: Internal clock never stabilised.\n", mmc_hostname(host->mmc)); > > + sdhci_dumpregs(host); > > + return 1; > > return -EIO; > I will update it to the V8 version. > > + } > > + return 0; > > +} > > + > > /*****************************************************************************\ > > * * > > * Driver init/exit * > Thanks, Victor Shih
diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index e2972be1889f..71ac76065886 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -14,6 +14,7 @@ #include <linux/module.h> #include <linux/iopoll.h> #include <linux/bitfield.h> +#include <linux/ktime.h> #include "sdhci.h" #include "sdhci-uhs2.h" @@ -328,6 +329,37 @@ static int sdhci_uhs2_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) return 0; } +static int sdhci_uhs2_disable_clk(struct mmc_host *mmc) +{ + struct sdhci_host *host = mmc_priv(mmc); + u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + + clk &= ~SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + return 0; +} + +static int sdhci_uhs2_enable_clk(struct mmc_host *mmc) +{ + struct sdhci_host *host = mmc_priv(mmc); + u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + u32 val; + /* 20ms */ + int timeout_us = 20000; + + clk |= SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + if (read_poll_timeout_atomic(sdhci_readw, val, (val & SDHCI_CLOCK_INT_STABLE), + 10, timeout_us, true, host, SDHCI_CLOCK_CONTROL)) { + pr_err("%s: Internal clock never stabilised.\n", mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return 1; + } + return 0; +} + /*****************************************************************************\ * * * Driver init/exit *