From patchwork Wed Mar 29 20:51:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sui Jingfeng <15330273260@189.cn> X-Patchwork-Id: 76814 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp684147vqo; Wed, 29 Mar 2023 14:02:30 -0700 (PDT) X-Google-Smtp-Source: AKy350Y4QK69aQzRklazW14q/U8CFRrbiEeU3yZ8CqSVQCqwcuVFNHe6acSlsSEStXXusOou2RNP X-Received: by 2002:a17:907:8c0e:b0:930:bc07:3bf7 with SMTP id ta14-20020a1709078c0e00b00930bc073bf7mr23668332ejc.5.1680123750470; Wed, 29 Mar 2023 14:02:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680123750; cv=none; d=google.com; s=arc-20160816; b=Fyko+a1qpRxEFB9KFLjH2+RpX4IKFl9CPtUEcIZTgmK2axzk808tZ8OG2FxoRiVw2X Brvz8C0dNf8ojgN9kX+uyhRaGo7ibnYyQQ6M2zO34EkM+UAGTnm+i6VjuaGAn8X8M7Op gLnFfR7h3zDZu+xqxjz8HCWoQmzjHjDKzBroiYXSlOlqMw5fToYeS8YJ0gN5/oxF42Z0 A8OjqvlhmZYlzuNCv+HKnXzQbhGLGALRe1gBMeglGRISNIC7gKIvTbSj25iXOoPPh1k/ 8qa/9aLcPvnWFPOcQkzQX7kOBLn348hDhKC04Tk63HUrAw211eSEYgH8vkm8snB2tgyw 7Yog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from:sender :hmm_source_type:hmm_attache_num:hmm_source_ip; bh=yqH0ILsc4kcWI5FhiPHvvoLOmwJ6Yb5/o8RSND1kjzo=; b=hS9SnysK+80HRFUCMhWTV3oMnZnEXkzw/EAHxEm7N9mramzrLvrp3jCQinTRoFwfoS 7P/cilBIV9iXwmjROED7jpPyuVbY3eSLPq+wKv1bcKf+X1cVeBLD6+m/nyRsGN/+GBM5 AmwzeHuG4nrgh25xMGZXCWp5v+oaOdaUCfUkK3JkPXD3KREgGjFxh4SE+YJuP99Y+Wnh kPoDBaA2bEbR9eLHdem2pIWTL4RoTbaJQLoswVNG8lWIyUm3m1rYl2nu08WrscRgHbMf aq+D8k1o+nB9N3ifWISi7N0oSToNdbZKoor/KNWUvt29L6HYtMBp/8KCWOroXsabCLa9 j4Ug== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id tl3-20020a170907c30300b00939ad72ecacsi22354930ejc.225.2023.03.29.14.01.58; Wed, 29 Mar 2023 14:02:30 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229934AbjC2Uvw (ORCPT + 99 others); Wed, 29 Mar 2023 16:51:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56678 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229564AbjC2Uvq (ORCPT ); Wed, 29 Mar 2023 16:51:46 -0400 Received: from 189.cn (ptr.189.cn [183.61.185.104]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 1A0D744B8 for ; Wed, 29 Mar 2023 13:51:44 -0700 (PDT) HMM_SOURCE_IP: 10.64.8.43:36106.2084148567 HMM_ATTACHE_NUM: 0000 HMM_SOURCE_TYPE: SMTP Received: from clientip-114.242.206.180 (unknown [10.64.8.43]) by 189.cn (HERMES) with SMTP id 61DE81002BE; Thu, 30 Mar 2023 04:51:42 +0800 (CST) Received: from ([114.242.206.180]) by gateway-151646-dep-7b48884fd-tj646 with ESMTP id 70aca06a346644b4bc2ecbeae02d8063 for l.stach@pengutronix.de; Thu, 30 Mar 2023 04:51:43 CST X-Transaction-ID: 70aca06a346644b4bc2ecbeae02d8063 X-Real-From: 15330273260@189.cn X-Receive-IP: 114.242.206.180 X-MEDUSA-Status: 0 Sender: 15330273260@189.cn From: Sui Jingfeng <15330273260@189.cn> To: Lucas Stach , Russell King , Christian Gmeiner , David Airlie , Daniel Vetter , Li Yi Cc: linux-kernel@vger.kernel.org, etnaviv@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Sui Jingfeng Subject: [PATCH v3 2/6] drm/etnaviv: add a dedicate function to get clock Date: Thu, 30 Mar 2023 04:51:25 +0800 Message-Id: <20230329205129.1513734-3-15330273260@189.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230329205129.1513734-1-15330273260@189.cn> References: <20230329205129.1513734-1-15330273260@189.cn> MIME-Version: 1.0 X-Spam-Status: No, score=0.6 required=5.0 tests=FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,FROM_LOCAL_DIGITS,FROM_LOCAL_HEX,SPF_HELO_PASS,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761737442068515733?= X-GMAIL-MSGID: =?utf-8?q?1761737442068515733?= From: Sui Jingfeng Because it is also platform dependent, there are environment which without clk subsystem support, we don't want the driver rage quit because of no clk subsystem driver support. There are discrete graphics card which integrate vivante gpu IP. For the GPU in ls7a1000 and lsak2000, working frequency of the gpu is changed by configuring the PLL register directly. Signed-off-by: Sui Jingfeng --- drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 62 ++++++++++++++++++--------- drivers/gpu/drm/etnaviv/etnaviv_gpu.h | 1 + 2 files changed, 42 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c index 636d3f39ddcb..4937580551a5 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c @@ -1565,10 +1565,45 @@ static irqreturn_t irq_handler(int irq, void *data) return ret; } +static int etnaviv_gpu_clk_get(struct etnaviv_gpu *gpu) +{ + struct device *dev = gpu->dev; + + if (gpu->no_clk) + return 0; + + gpu->clk_reg = devm_clk_get_optional(dev, "reg"); + DBG("clk_reg: %p", gpu->clk_reg); + if (IS_ERR(gpu->clk_reg)) + return PTR_ERR(gpu->clk_reg); + + gpu->clk_bus = devm_clk_get_optional(dev, "bus"); + DBG("clk_bus: %p", gpu->clk_bus); + if (IS_ERR(gpu->clk_bus)) + return PTR_ERR(gpu->clk_bus); + + gpu->clk_core = devm_clk_get(dev, "core"); + DBG("clk_core: %p", gpu->clk_core); + if (IS_ERR(gpu->clk_core)) + return PTR_ERR(gpu->clk_core); + gpu->base_rate_core = clk_get_rate(gpu->clk_core); + + gpu->clk_shader = devm_clk_get_optional(dev, "shader"); + DBG("clk_shader: %p", gpu->clk_shader); + if (IS_ERR(gpu->clk_shader)) + return PTR_ERR(gpu->clk_shader); + gpu->base_rate_shader = clk_get_rate(gpu->clk_shader); + + return 0; +} + static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu) { int ret; + if (gpu->no_clk) + return 0; + ret = clk_prepare_enable(gpu->clk_reg); if (ret) return ret; @@ -1599,6 +1634,9 @@ static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu) static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu) { + if (gpu->no_clk) + return 0; + clk_disable_unprepare(gpu->clk_shader); clk_disable_unprepare(gpu->clk_core); clk_disable_unprepare(gpu->clk_bus); @@ -1865,27 +1903,9 @@ static int etnaviv_gpu_platform_probe(struct platform_device *pdev) return err; /* Get Clocks: */ - gpu->clk_reg = devm_clk_get_optional(&pdev->dev, "reg"); - DBG("clk_reg: %p", gpu->clk_reg); - if (IS_ERR(gpu->clk_reg)) - return PTR_ERR(gpu->clk_reg); - - gpu->clk_bus = devm_clk_get_optional(&pdev->dev, "bus"); - DBG("clk_bus: %p", gpu->clk_bus); - if (IS_ERR(gpu->clk_bus)) - return PTR_ERR(gpu->clk_bus); - - gpu->clk_core = devm_clk_get(&pdev->dev, "core"); - DBG("clk_core: %p", gpu->clk_core); - if (IS_ERR(gpu->clk_core)) - return PTR_ERR(gpu->clk_core); - gpu->base_rate_core = clk_get_rate(gpu->clk_core); - - gpu->clk_shader = devm_clk_get_optional(&pdev->dev, "shader"); - DBG("clk_shader: %p", gpu->clk_shader); - if (IS_ERR(gpu->clk_shader)) - return PTR_ERR(gpu->clk_shader); - gpu->base_rate_shader = clk_get_rate(gpu->clk_shader); + err = etnaviv_gpu_clk_get(gpu); + if (err) + return err; /* TODO: figure out max mapped size */ dev_set_drvdata(dev, gpu); diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.h b/drivers/gpu/drm/etnaviv/etnaviv_gpu.h index 98c6f9c320fc..6da5209a7d64 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.h +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.h @@ -148,6 +148,7 @@ struct etnaviv_gpu { struct clk *clk_reg; struct clk *clk_core; struct clk *clk_shader; + bool no_clk; unsigned int freq_scale; unsigned long base_rate_core;