Message ID | 20230329084744.5705-9-quic_jinlmao@quicinc.com |
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State | New |
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Wed, 29 Mar 2023 08:48:00 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 32T8lxwR023421 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Mar 2023 08:47:59 GMT Received: from hu-jinlmao-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Wed, 29 Mar 2023 01:47:58 -0700 From: Mao Jinlong <quic_jinlmao@quicinc.com> To: Alexander Shishkin <alexander.shishkin@linux.intel.com>, Andy Gross <agross@kernel.org>, Bjorn Andersson <andersson@kernel.org>, Konrad Dybcio <konrad.dybcio@linaro.org>, Mathieu Poirier <mathieu.poirier@linaro.org>, Suzuki K Poulose <suzuki.poulose@arm.com>, Mike Leach <mike.leach@linaro.org>, Leo Yan <leo.yan@linaro.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> CC: Mao Jinlong <quic_jinlmao@quicinc.com>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <coresight@lists.linaro.org>, <devicetree@vger.kernel.org>, <linux-arm-msm@vger.kernel.org>, Tingwei Zhang <quic_tingweiz@quicinc.com>, Yuanfang Zhang <quic_yuanfang@quicinc.com>, Tao Zhang <quic_taozha@quicinc.com>, Hao Zhang <quic_hazha@quicinc.com> Subject: [PATCH v1 8/8] dt-bindings: arm: Add support for TPDM CMB element size Date: Wed, 29 Mar 2023 01:47:44 -0700 Message-ID: <20230329084744.5705-9-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230329084744.5705-1-quic_jinlmao@quicinc.com> References: <20230329084744.5705-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: GLsgeYYQQ4AB4XtBOcZqp0R4KauqzKhs X-Proofpoint-ORIG-GUID: GLsgeYYQQ4AB4XtBOcZqp0R4KauqzKhs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-29_02,2023-03-28_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=831 impostorscore=0 phishscore=0 mlxscore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 clxscore=1015 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2303290071 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761691769029070135?= X-GMAIL-MSGID: =?utf-8?q?1761691769029070135?= |
Series |
Add cmb dataset support for TPDM
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Commit Message
Mao Jinlong
March 29, 2023, 8:47 a.m. UTC
Add property "qcom,cmb-elem-size" to support CMB element for TPDM.
The associated aggregator will read this size before it is enabled.
CMB element size currently only supports 8-bit, 32-bit and 64-bit.
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
---
.../bindings/arm/qcom,coresight-tpdm.yaml | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
Comments
On 29/03/2023 10:47, Mao Jinlong wrote: > Add property "qcom,cmb-elem-size" to support CMB element for TPDM. > The associated aggregator will read this size before it is enabled. > CMB element size currently only supports 8-bit, 32-bit and 64-bit. > > Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com> > --- > .../bindings/arm/qcom,coresight-tpdm.yaml | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml > index 283dfb39d46f..c5169de81e58 100644 > --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml > +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml > @@ -53,6 +53,14 @@ properties: > minimum: 32 > maximum: 64 > > + qcom,cmb-element-size: s/size/bits/ https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/property-units.yaml > + description: > + Specifies the CMB (Continuous multi-bit) element size supported by > + the monitor. The associated aggregator will read this size before it > + is enabled. CMB element size currently supports 8-bit, 32-bit, 64-bit. > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [8, 32, 64] > + > qcom,dsb_msr_num: > description: > Specifies the number of DSB(Discrete Single Bit) MSR(mux select register) > @@ -95,6 +103,12 @@ required: > - clocks > - clock-names > > +anyOf: > + - required: > + - qcom,dsb_msr_num There is no such property. > + - required: > + - qcom,cmb-msr-num Why this is part of this patch? > + > additionalProperties: false > > examples: > @@ -105,6 +119,8 @@ examples: > reg = <0x0684c000 0x1000>; > > qcom,dsb-element-size = <32>; > + qcom,cmb-element-size = <32>; > + > qcom,dsb_msr_num = <16>; > qcom,cmb-msr-num = <6>; > Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml index 283dfb39d46f..c5169de81e58 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml @@ -53,6 +53,14 @@ properties: minimum: 32 maximum: 64 + qcom,cmb-element-size: + description: + Specifies the CMB (Continuous multi-bit) element size supported by + the monitor. The associated aggregator will read this size before it + is enabled. CMB element size currently supports 8-bit, 32-bit, 64-bit. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [8, 32, 64] + qcom,dsb_msr_num: description: Specifies the number of DSB(Discrete Single Bit) MSR(mux select register) @@ -95,6 +103,12 @@ required: - clocks - clock-names +anyOf: + - required: + - qcom,dsb_msr_num + - required: + - qcom,cmb-msr-num + additionalProperties: false examples: @@ -105,6 +119,8 @@ examples: reg = <0x0684c000 0x1000>; qcom,dsb-element-size = <32>; + qcom,cmb-element-size = <32>; + qcom,dsb_msr_num = <16>; qcom,cmb-msr-num = <6>;