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From: Mao Jinlong <quic_jinlmao@quicinc.com>
To: Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
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<devicetree@vger.kernel.org>, <linux-arm-msm@vger.kernel.org>,
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Yuanfang Zhang <quic_yuanfang@quicinc.com>,
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Subject: [PATCH v1 6/8] dt-bindings: arm: Add support for TPDM CMB MSR
register
Date: Wed, 29 Mar 2023 01:47:42 -0700
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|
| Series |
Add cmb dataset support for TPDM
|
|
Commit Message
Mao Jinlong
March 29, 2023, 8:47 a.m. UTC
Add property "qcom,cmb_msr_num" to support CMB MSR(mux select register)
for TPDM. It specifies the number of CMB MSR registers supported by
the TDPM.
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
---
.../devicetree/bindings/arm/qcom,coresight-tpdm.yaml | 10 ++++++++++
1 file changed, 10 insertions(+)
Comments
On 29/03/2023 10:47, Mao Jinlong wrote: > Add property "qcom,cmb_msr_num" to support CMB MSR(mux select register) > for TPDM. It specifies the number of CMB MSR registers supported by > the TDPM. > > Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml index 691c7ba365aa..283dfb39d46f 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml @@ -62,6 +62,15 @@ properties: minimum: 0 maximum: 32 + qcom,cmb-msr-num: + description: + Specifies the number of CMB MSR(mux select register) + registers supported by the monitor. If this property is not configured + or set to 0, it means this TPDM doesn't support CMB MSR. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 128 + clocks: maxItems: 1 @@ -97,6 +106,7 @@ examples: qcom,dsb-element-size = <32>; qcom,dsb_msr_num = <16>; + qcom,cmb-msr-num = <6>; clocks = <&aoss_qmp>; clock-names = "apb_pclk";