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[1/4] arm64: dts: qcom: msm8998: Improve GPU OPP table

Message ID 20230329-topic-adreno_opp-v1-1-24d34ac6f007@linaro.org
State New
Headers
Series Improve some Adreno Device Tree nodes |

Commit Message

Konrad Dybcio March 29, 2023, 7:17 p.m. UTC 
  Add a newline before the first OPP subnode, remove useless
opp-supported-hw (there's only a single speed bin anyway) and replace
opp-level with required-opps to make sure the power domain level is
actually set, as opp-level is not the right property for this..
Furthermore, correct the levels that were incorrect before (confirmed
against downstream).

Round off frequencies that had uneven fluff on the last two digits.

To top if off, leave a note that we should really be scaling the
VDD GFX power domain coming from CPR4, which is not yet supported.
Scaling MX is still very important though and can be considered
valid for the time being - it's better if we scale at one of
two voltage rails than if we scaled none..

Fixes: 87cd46d68aea ("arm64: dts: qcom: msm8998: Configure Adreno GPU and related IOMMU")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/msm8998.dtsi | 39 +++++++++++++++--------------------
 1 file changed, 17 insertions(+), 22 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index 09b222f363c2..11952f9ed9ae 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -1396,51 +1396,46 @@  adreno_gpu: gpu@5000000 {
 			interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
 			iommus = <&adreno_smmu 0>;
 			operating-points-v2 = <&gpu_opp_table>;
+			/* TODO: also scale VDDGFX with CPR4 */
 			power-domains = <&rpmpd MSM8998_VDDMX>;
 			status = "disabled";
 
 			gpu_opp_table: opp-table {
 				compatible = "operating-points-v2";
-				opp-710000097 {
-					opp-hz = /bits/ 64 <710000097>;
-					opp-level = <RPM_SMD_LEVEL_TURBO>;
-					opp-supported-hw = <0xff>;
+
+				opp-710000000 {
+					opp-hz = /bits/ 64 <710000000>;
+					required-opps = <&rpmpd_opp_turbo>;
 				};
 
-				opp-670000048 {
-					opp-hz = /bits/ 64 <670000048>;
-					opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
-					opp-supported-hw = <0xff>;
+				opp-670000000 {
+					opp-hz = /bits/ 64 <670000000>;
+					required-opps = <&rpmpd_opp_turbo>;
 				};
 
-				opp-596000097 {
-					opp-hz = /bits/ 64 <596000097>;
-					opp-level = <RPM_SMD_LEVEL_NOM>;
-					opp-supported-hw = <0xff>;
+				opp-596000000 {
+					opp-hz = /bits/ 64 <596000000>;
+					required-opps = <&rpmpd_opp_nom>;
 				};
 
-				opp-515000097 {
-					opp-hz = /bits/ 64 <515000097>;
-					opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
-					opp-supported-hw = <0xff>;
+				opp-515000000 {
+					opp-hz = /bits/ 64 <515000000>;
+					required-opps = <&rpmpd_opp_nom>;
 				};
 
 				opp-414000000 {
 					opp-hz = /bits/ 64 <414000000>;
-					opp-level = <RPM_SMD_LEVEL_SVS>;
-					opp-supported-hw = <0xff>;
+					required-opps = <&rpmpd_opp_svs>;
 				};
 
 				opp-342000000 {
 					opp-hz = /bits/ 64 <342000000>;
-					opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
-					opp-supported-hw = <0xff>;
+					required-opps = <&rpmpd_opp_svs>;
 				};
 
 				opp-257000000 {
 					opp-hz = /bits/ 64 <257000000>;
-					opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
-					opp-supported-hw = <0xff>;
+					required-opps = <&rpmpd_opp_svs>;
 				};
 			};
 		};