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[83.9.3.225]) by smtp.gmail.com with ESMTPSA id f10-20020ac24e4a000000b004db3e330dcesm5008471lfr.178.2023.03.28.03.03.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Mar 2023 03:03:01 -0700 (PDT) From: Konrad Dybcio Date: Tue, 28 Mar 2023 12:02:52 +0200 Subject: [PATCH 1/2] dt-bindings: interrupt-controller: mpm: Allow passing reg through phandle MIME-Version: 1.0 Message-Id: <20230328-topic-msgram_mpm-v1-1-1b788a5f5a33@linaro.org> References: <20230328-topic-msgram_mpm-v1-0-1b788a5f5a33@linaro.org> In-Reply-To: <20230328-topic-msgram_mpm-v1-0-1b788a5f5a33@linaro.org> To: Andy Gross , Bjorn Andersson , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Shawn Guo Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1679997779; l=1381; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=C4N0Ev8VKX3zoI5LrzMOtOGVDcPvF0sVmEyLrmGffDM=; b=5VTz0TXYou6dESAd20JbdSqHQfvEqtSex/DVC7nsLbDDDFk1MRXmIhegfP3UUOj0Hwa28Li2VIg9 7jVFDEIBCvVhPHyP1gldQPvO0g3ZxbeD9i8Zi4xH2OVWQZcnicj1 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761605627819644216?= X-GMAIL-MSGID: =?utf-8?q?1761605627819644216?= Due to the wild nature of the Qualcomm RPM Message RAM, we can't really use 'reg' to point to the MPM's slice of Message RAM without cutting into an already-defined RPM MSG RAM node used for GLINK and SMEM. Document passing the register space as a slice of SRAM through the qcom,rpm-msg-ram property. This also makes 'reg' no longer required. Signed-off-by: Konrad Dybcio --- .../devicetree/bindings/interrupt-controller/qcom,mpm.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml index 509d20c091af..77fe5e0b378f 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml @@ -30,6 +30,11 @@ properties: description: Specifies the base address and size of vMPM registers in RPM MSG RAM. + qcom,rpm-msg-ram: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the APSS MPM slice of the RPM Message RAM + interrupts: maxItems: 1 description: @@ -64,7 +69,6 @@ properties: required: - compatible - - reg - interrupts - mboxes - interrupt-controller