| Message ID | 20230327083647.22017-4-angelogioacchino.delregno@collabora.com |
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From: AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>
To: matthias.bgg@gmail.com
Cc: qii.wang@mediatek.com, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, jassisinghbrar@gmail.com,
houlong.wei@mediatek.com, linux-i2c@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, kernel@collabora.com,
phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>
Subject: [PATCH v2 03/17] arm64: dts: mediatek: mt6795: xperia-m5: Enable
Frequency Hopping
Date: Mon, 27 Mar 2023 10:36:33 +0200
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|
| Series |
MT6795 Helio X10 and Sony Xperia M5: DT step 2!
|
|
Commit Message
AngeloGioacchino Del Regno
March 27, 2023, 8:36 a.m. UTC
Enable FHCTL with Spread Spectrum for MAINPLL, MPLL and MSDCPLL
as found on the downstream kernel for this smartphone.
Which one to enable, and at what SSC percentage, was found by
dumping the debugging data from a running downstream kernel and
checking the downstream code.
/proc/freqhopping # cat status
FH status:
===============================================
id == fh_status == pll_status == setting_id == curr_freq == user_defined
0 0 1 0 1599000 0
1 0 1 0 1716000 0
2 1 1 2 1092000 0
3 1 1 2 2912000 0
4 1 0 2 1600000 0
5 0 0 0 0 0
6 0 1 0 1518002 0
7 0 0 0 0 0
8 0 0 0 0 0
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts index d3415527d389..52ce3284a46f 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts +++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts @@ -48,6 +48,13 @@ bootloader-region@46000000 { }; }; +&fhctl { + clocks = <&apmixedsys CLK_APMIXED_MAINPLL>, <&apmixedsys CLK_APMIXED_MPLL>, + <&apmixedsys CLK_APMIXED_MSDCPLL>; + mediatek,hopping-ssc-percent = <8>, <5>, <8>; + status = "okay"; +}; + &pio { uart0_pins: uart0-pins { pins-rx {