From patchwork Mon Mar 27 07:58:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 75257 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1352303vqo; Mon, 27 Mar 2023 01:26:01 -0700 (PDT) X-Google-Smtp-Source: AK7set9I7kXIBR1x/E1ko6uX6mLWJsJMawtdlpajcuu8VcVjCt/vNAv0C2HhDEv1FWJewxQkCJi9 X-Received: by 2002:a05:6a20:6d27:b0:d9:2827:b65a with SMTP id fv39-20020a056a206d2700b000d92827b65amr10824852pzb.5.1679905561543; Mon, 27 Mar 2023 01:26:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1679905561; cv=none; d=google.com; s=arc-20160816; b=l2Nl2lNxFsBRX6v9a2q7BqBUs/u2zk3s6aYUv0WFJAsb6v2Zi5VRC0K6uerxClOkNw 0TeGy0K2yvITSOFEV4cObPKzmc/TFCkwyh0CnP95aE4Ksb/s844lUaLgvQ11f00DYoNA RKvaRbY9VlQMKBxg/dThdSDxYX2iWfk7qK7A21yeFcc//vsuWzpSrBA1ZMhwDGqLlXc0 Kgq/aMugrg5N6RlhhXXx+WUlf5vNximWpzzqTcewvk7fcqau0b3jH/r4693YrG4o/jPV PTHcOkq0hGlAbqqKIym9pUAF/5aXyPcry8m1udE3aG/+Vnu7y+LbyDFtIJTjzyjr3SOb mWCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=s1TnurdU9eI1YRCwil5WMrFTmYZQx9ZLxqgiOpLcQhQ=; b=z+FGoI26JIxakNG6RH9I3FxgS8w8eZaw4Jd2K/Kit8N1snHZhaBkxt+Tk/pxQWf8EW 8ksDbhfIxf8cHZ4XyfZPkx2WBGkPM2vXO6H5Ud54lDtDoSNaIy7uYNPzsY4olM0oeOY8 Tkwc+x40xblKcKPn4QNBg8nBLA50HX62wLnGEY5jAyzC6lY3C86eh/u/8hvfqpdwvmdy MJESxsfIe5mBG6XKHiW9+hTb8bODiqLUTKoolUI/jAPLJlbV8L0/R8Ubdle8i0lP8Mnx LuNaYubK5q4C+lxNmLkwwxcX+wARej2SHwzU0WaWQVzegRImKzHB0jzkMABNXYUJu4EW 1h8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=m6CNPt6I; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id d3-20020a056a00244300b005a8b856ad47si27117497pfj.7.2023.03.27.01.25.48; Mon, 27 Mar 2023 01:26:01 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=m6CNPt6I; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233108AbjC0IZD (ORCPT + 99 others); Mon, 27 Mar 2023 04:25:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59624 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232938AbjC0IYe (ORCPT ); Mon, 27 Mar 2023 04:24:34 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F35F2D57; Mon, 27 Mar 2023 01:24:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1679905473; x=1711441473; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=g68cyMdX2debPTjgjq16HL+D6AhwC/hj42OGPtnTvek=; b=m6CNPt6IPMO+2Wpk8wDqph8p+THn6N3vu//8K7kuPiqBrOsVhTxzer9T X8qU5ILzWATOX2jw9I4NEuryoAlb+P0uGyStlGCi+VVtVMviIhJAE/XpC m3lEXNjVoreC185e2xtAZtrm6HJGQvPkTIbYcSqM1Ui6CIZ0TpHR9A3xv UIHUJ7PnYb9O7zb86BlY9bJF9mcc2i7d+55TT6SuQAcIF691QDNMDIJBB AmvvPcfSiNMk10X5LU8i+FnrHsDg0WiAq0795SPN+TiJKMkqUOi5UTr/7 KCLRLqiHfvL++utVIoZT790E73sc2K+WbHC2jiXfPHx686iyCyZsoXIix w==; X-IronPort-AV: E=McAfee;i="6600,9927,10661"; a="338930137" X-IronPort-AV: E=Sophos;i="5.98,294,1673942400"; d="scan'208";a="338930137" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Mar 2023 01:24:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10661"; a="713787049" X-IronPort-AV: E=Sophos;i="5.98,294,1673942400"; d="scan'208";a="713787049" Received: from unknown (HELO fred..) ([172.25.112.68]) by orsmga008.jf.intel.com with ESMTP; 27 Mar 2023 01:24:31 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v6 06/33] x86/cpufeature: add the cpu feature bit for FRED Date: Mon, 27 Mar 2023 00:58:11 -0700 Message-Id: <20230327075838.5403-7-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230327075838.5403-1-xin3.li@intel.com> References: <20230327075838.5403-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761508653767223730?= X-GMAIL-MSGID: =?utf-8?q?1761508653767223730?= From: "H. Peter Anvin (Intel)" Add the CPU feature bit for FRED (Flexible Return and Event Delivery). The Intel flexible return and event delivery (FRED) architecture defines simple new transitions that change privilege level (ring transitions). The FRED architecture was designed with the following goals: 1) Improve overall performance and response time by replacing event delivery through the interrupt descriptor table (IDT event delivery) and event return by the IRET instruction with lower latency transitions. 2) Improve software robustness by ensuring that event delivery establishes the full supervisor context and that event return establishes the full user context. The new transitions defined by the FRED architecture are FRED event delivery and, for returning from events, two FRED return instructions. FRED event delivery can effect a transition from ring 3 to ring 0, but it is used also to deliver events incident to ring 0. One FRED instruction (ERETU) effects a return from ring 0 to ring 3, while the other (ERETS) returns while remaining in ring 0. Search for the latest FRED spec in most search engines with this search pattern: site:intel.com FRED (flexible return and event delivery) specification Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/asm/cpufeatures.h | 1 + tools/arch/x86/include/asm/cpufeatures.h | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 73c9672c123b..1fa444478d33 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -318,6 +318,7 @@ #define X86_FEATURE_FZRM (12*32+10) /* "" Fast zero-length REP MOVSB */ #define X86_FEATURE_FSRS (12*32+11) /* "" Fast short REP STOSB */ #define X86_FEATURE_FSRC (12*32+12) /* "" Fast short REP {CMPSB,SCASB} */ +#define X86_FEATURE_FRED (12*32+17) /* Flexible Return and Event Delivery */ #define X86_FEATURE_LKGS (12*32+18) /* "" Load "kernel" (userspace) GS */ #define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */ #define X86_FEATURE_AVX_IFMA (12*32+23) /* "" Support for VPMADD52[H,L]UQ */ diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h index b89005819cd5..e9064f4a011a 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -312,6 +312,7 @@ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */ #define X86_FEATURE_CMPCCXADD (12*32+ 7) /* "" CMPccXADD instructions */ +#define X86_FEATURE_FRED (12*32+17) /* Flexible Return and Event Delivery */ #define X86_FEATURE_LKGS (12*32+18) /* "" Load "kernel" (userspace) GS */ #define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */ #define X86_FEATURE_AVX_IFMA (12*32+23) /* "" Support for VPMADD52[H,L]UQ */