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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id q204-20020a4a33d5000000b0053853156b5csm11154922ooq.8.2023.03.27.11.43.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 11:43:22 -0700 (PDT) Received: (nullmailer pid 250781 invoked by uid 1000); Mon, 27 Mar 2023 18:43:19 -0000 From: Rob Herring Date: Mon, 27 Mar 2023 13:43:20 -0500 Subject: [PATCH 3/3] clk: mvebu: Iterate over possible CPUs instead of DT CPU nodes MIME-Version: 1.0 Message-Id: <20230327-mvebu-clk-fixes-v1-3-438de1026efd@kernel.org> References: <20230327-mvebu-clk-fixes-v1-0-438de1026efd@kernel.org> In-Reply-To: <20230327-mvebu-clk-fixes-v1-0-438de1026efd@kernel.org> To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org X-Mailer: b4 0.13-dev X-Spam-Status: No, score=0.8 required=5.0 tests=FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761548341778040883?= X-GMAIL-MSGID: =?utf-8?q?1761548341778040883?= Rework iterating over DT CPU nodes to iterate over possible CPUs instead. There's no need to walk the DT CPU nodes again. Possible CPUs is equal to the number of CPUs defined in the DT. Using the "reg" value for an array index is fragile as it assumes "reg" is 0-N which often is not the case. Signed-off-by: Rob Herring --- drivers/clk/mvebu/clk-cpu.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/clk/mvebu/clk-cpu.c b/drivers/clk/mvebu/clk-cpu.c index c2af3395cf13..db2b38c21304 100644 --- a/drivers/clk/mvebu/clk-cpu.c +++ b/drivers/clk/mvebu/clk-cpu.c @@ -168,8 +168,8 @@ static void __init of_cpu_clk_setup(struct device_node *node) struct cpu_clk *cpuclk; void __iomem *clock_complex_base = of_iomap(node, 0); void __iomem *pmu_dfs_base = of_iomap(node, 1); - int ncpus = 0; - struct device_node *dn; + int ncpus = num_possible_cpus(); + int cpu; if (clock_complex_base == NULL) { pr_err("%s: clock-complex base register not set\n", @@ -181,9 +181,6 @@ static void __init of_cpu_clk_setup(struct device_node *node) pr_warn("%s: pmu-dfs base register not set, dynamic frequency scaling not available\n", __func__); - for_each_of_cpu_node(dn) - ncpus++; - cpuclk = kcalloc(ncpus, sizeof(*cpuclk), GFP_KERNEL); if (WARN_ON(!cpuclk)) goto cpuclk_out; @@ -192,19 +189,14 @@ static void __init of_cpu_clk_setup(struct device_node *node) if (WARN_ON(!clks)) goto clks_out; - for_each_of_cpu_node(dn) { + for_each_possible_cpu(cpu) { struct clk_init_data init; struct clk *clk; char *clk_name = kzalloc(5, GFP_KERNEL); - int cpu, err; if (WARN_ON(!clk_name)) goto bail_out; - err = of_property_read_u32(dn, "reg", &cpu); - if (WARN_ON(err)) - goto bail_out; - sprintf(clk_name, "cpu%d", cpu); cpuclk[cpu].parent_name = of_clk_get_parent_name(node, 0);