Message ID | 20230324160918.826452-1-christophe.kerello@foss.st.com |
---|---|
State | New |
Headers |
Return-Path: <linux-kernel-owner@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp750392vqo; Fri, 24 Mar 2023 09:23:19 -0700 (PDT) X-Google-Smtp-Source: AKy350aaRveEMpALzai51Iqb1pq2nCzV486p/fF7U4e5FN7TGc3uS5ZhRtxfh3JUsP9yxnB5UP5b X-Received: by 2002:a17:906:3616:b0:931:19f8:d89c with SMTP id q22-20020a170906361600b0093119f8d89cmr3188632ejb.73.1679674998882; Fri, 24 Mar 2023 09:23:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1679674998; cv=none; d=google.com; s=arc-20160816; b=jdHufkTS0qHopJqA1gcdJTtEmCYy6lcO8q+cYXntz8KyBrymjdJgr0UdO0pg/aXSit W02gRuVVS9H3UemU09fq91F53M1tlRU1xSGd7oR4sXYGn9q71s2zm0v1koHMwakLoz2y AMc1fDrVd1QH5ZeqA9flGpJzIertJ5JB1jAVUS357UZOIvfaGDcRwEI8CuW9psTQPzJ4 wIMqMKJ0F5MfFsHl/hMj3c1ROVpQSOlurwVJsMuJazPPDQEr8LPbWtcezp6EblZ1uWa6 dpyXWsAwkrCQl58/lemr9XZZR8fxEJhoFu5prr5XoyKqBP6D6B3isj6Ns+J6FpHJpl2E Vtuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=WYV7EBAofXJyjzZBSfwpOR5v4z00FX931Kh4b0ja95g=; b=ZIhipqrvjlNVfOXgkkrdWUbc0uoEGmxiQ0xdDZ2CuMgIhQ8Y4qgEO/KABlCxlV4oLT w9hX17ecXJdFviBMaLanYzQQjIg1W1OBdR8W+lp63U+gJN7+Mhh/QlVOBm8V86shNDtg U3tSjSKQbNQkD+ALcHslELPKPG9VXH68leIgcZJ7n96gpE/OtZEICkvAlxZiWhOKU2JR 2bSBxwGyLcKJS2cyqxEAFWTwpCZZHiHljH5SlYYUky9GXrgSXe69v3/XJCK/iOhDVRNO CDXlbbYDoJesrcuak3tR8Gr7wRxJmCrtZ+WtpkcbAyz0Iu4VTcXVtQ8gNfdGz39egH5Q 9L+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=ouywm90f; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id z21-20020aa7cf95000000b005002d86f446si22157387edx.128.2023.03.24.09.22.54; Fri, 24 Mar 2023 09:23:18 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=ouywm90f; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231282AbjCXQJx (ORCPT <rfc822;makky5685@gmail.com> + 99 others); Fri, 24 Mar 2023 12:09:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231395AbjCXQJs (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Fri, 24 Mar 2023 12:09:48 -0400 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64ED519F0A for <linux-kernel@vger.kernel.org>; Fri, 24 Mar 2023 09:09:44 -0700 (PDT) Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32ODf4MG027124; Fri, 24 Mar 2023 17:09:27 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=selector1; bh=WYV7EBAofXJyjzZBSfwpOR5v4z00FX931Kh4b0ja95g=; b=ouywm90fgp4EGgxeJehtG2Dg+r7UyC/vqM0ZumAEMaf/m1ZYnVM+2WIa8SAISi7j2Oxl ihTIGYZOJHZv1//u93ylVxRIjQ71XvXKP2CwUvAcQKdmjijgDakPRalkCbaO9ZErKJTt I8Wo7O3m772HxZG9DuIaBDqkIKrzM3D8JXBnKFAwtlttSOVHvURzr+goQIBzZ9TAQ2ik CCPbQJ4u96Lf4+8rbBte4b5ALIUlPEkI+moqNIGHLjVANvFiteZXp5uiGI5z2AUttwcB X5tlR7QqLtTtpLSn1fuEHU+0zsyWsF3ZgOSU11DLsmZ5WHwht8CHj9UKO6TuhNDHbu60 XQ== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3pgxhx5wdt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 24 Mar 2023 17:09:27 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 0C599100034; Fri, 24 Mar 2023 17:09:27 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 0697321A20B; Fri, 24 Mar 2023 17:09:27 +0100 (CET) Received: from localhost (10.48.0.175) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.17; Fri, 24 Mar 2023 17:09:26 +0100 From: Christophe Kerello <christophe.kerello@foss.st.com> To: <miquel.raynal@bootlin.com>, <richard@nod.at>, <vigneshr@ti.com> CC: <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-stm32@st-md-mailman.stormreply.com>, Christophe Kerello <christophe.kerello@foss.st.com> Subject: [PATCH] mtd: rawnand: stm32_fmc2: do not support EDO mode Date: Fri, 24 Mar 2023 17:09:18 +0100 Message-ID: <20230324160918.826452-1-christophe.kerello@foss.st.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.48.0.175] X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-24_10,2023-03-24_01,2023-02-09_01 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761266891599301153?= X-GMAIL-MSGID: =?utf-8?q?1761266891599301153?= |
Series |
mtd: rawnand: stm32_fmc2: do not support EDO mode
|
|
Commit Message
Christophe Kerello
March 24, 2023, 4:09 p.m. UTC
FMC2 controller does not support EDO mode (timings mode 4 and 5).
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Fixes: 2cd457f328c1 ("mtd: rawnand: stm32_fmc2: add STM32 FMC2 NAND flash controller driver")
---
drivers/mtd/nand/raw/stm32_fmc2_nand.c | 3 +++
1 file changed, 3 insertions(+)
Comments
Hi Christophe, christophe.kerello@foss.st.com wrote on Fri, 24 Mar 2023 17:09:18 +0100: > FMC2 controller does not support EDO mode (timings mode 4 and 5). > > Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> > Fixes: 2cd457f328c1 ("mtd: rawnand: stm32_fmc2: add STM32 FMC2 NAND flash controller driver") > --- > drivers/mtd/nand/raw/stm32_fmc2_nand.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c > index 5d627048c420..3abb63d00a0b 100644 > --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c > +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c > @@ -1531,6 +1531,9 @@ static int stm32_fmc2_nfc_setup_interface(struct nand_chip *chip, int chipnr, > if (IS_ERR(sdrt)) > return PTR_ERR(sdrt); > > + if (sdrt->tRC_min < 30000) When introducing NV-DDR support we as well added a timings.mode field, perhaps you could use it? > + return -EOPNOTSUPP; > + > if (chipnr == NAND_DATA_IFACE_CHECK_ONLY) > return 0; > Thanks, Miquèl
Hello Miquel, On 3/24/23 17:25, Miquel Raynal wrote: > Hi Christophe, > > christophe.kerello@foss.st.com wrote on Fri, 24 Mar 2023 17:09:18 +0100: > >> FMC2 controller does not support EDO mode (timings mode 4 and 5). >> >> Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> >> Fixes: 2cd457f328c1 ("mtd: rawnand: stm32_fmc2: add STM32 FMC2 NAND flash controller driver") >> --- >> drivers/mtd/nand/raw/stm32_fmc2_nand.c | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c >> index 5d627048c420..3abb63d00a0b 100644 >> --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c >> +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c >> @@ -1531,6 +1531,9 @@ static int stm32_fmc2_nfc_setup_interface(struct nand_chip *chip, int chipnr, >> if (IS_ERR(sdrt)) >> return PTR_ERR(sdrt); >> >> + if (sdrt->tRC_min < 30000) > > When introducing NV-DDR support we as well added a timings.mode field, > perhaps you could use it? Yes, I can use it. It will be done in V2. Regards, Christophe Kerello. > >> + return -EOPNOTSUPP; >> + >> if (chipnr == NAND_DATA_IFACE_CHECK_ONLY) >> return 0; >> > > > Thanks, > Miquèl
Hello Miquel, On 3/24/23 17:34, Christophe Kerello wrote: > Hello Miquel, > > On 3/24/23 17:25, Miquel Raynal wrote: >> Hi Christophe, >> >> christophe.kerello@foss.st.com wrote on Fri, 24 Mar 2023 17:09:18 +0100: >> >>> FMC2 controller does not support EDO mode (timings mode 4 and 5). >>> >>> Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> >>> Fixes: 2cd457f328c1 ("mtd: rawnand: stm32_fmc2: add STM32 FMC2 NAND >>> flash controller driver") >>> --- >>> drivers/mtd/nand/raw/stm32_fmc2_nand.c | 3 +++ >>> 1 file changed, 3 insertions(+) >>> >>> diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c >>> b/drivers/mtd/nand/raw/stm32_fmc2_nand.c >>> index 5d627048c420..3abb63d00a0b 100644 >>> --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c >>> +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c >>> @@ -1531,6 +1531,9 @@ static int >>> stm32_fmc2_nfc_setup_interface(struct nand_chip *chip, int chipnr, >>> if (IS_ERR(sdrt)) >>> return PTR_ERR(sdrt); >>> + if (sdrt->tRC_min < 30000) >> >> When introducing NV-DDR support we as well added a timings.mode field, >> perhaps you could use it? > > Yes, I can use it. It will be done in V2. > > Regards, > Christophe Kerello. > I had a look at Kernel LTS, and timings.mode was introduced on Kernel LTS 5.10. As this patch has also to be applied on Kernel LTS 5.4, my proposal is to send a new patch set. The first patch will be the current patch (fix for all Kernel LTS) and the second patch will use timings.mode instead of checking tRC_min timings for next Kernel delivery. Is this proposal acceptable? Regards, Christophe Kerello. >> >>> + return -EOPNOTSUPP; >>> + >>> if (chipnr == NAND_DATA_IFACE_CHECK_ONLY) >>> return 0; >> >> >> Thanks, >> Miquèl
Hi Christophe, christophe.kerello@foss.st.com wrote on Mon, 27 Mar 2023 10:02:13 +0200: > Hello Miquel, > > On 3/24/23 17:34, Christophe Kerello wrote: > > Hello Miquel, > > > > On 3/24/23 17:25, Miquel Raynal wrote: > >> Hi Christophe, > >> > >> christophe.kerello@foss.st.com wrote on Fri, 24 Mar 2023 17:09:18 +0100: > >> > >>> FMC2 controller does not support EDO mode (timings mode 4 and 5). > >>> > >>> Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> > >>> Fixes: 2cd457f328c1 ("mtd: rawnand: stm32_fmc2: add STM32 FMC2 NAND >>> flash controller driver") > >>> --- > >>> drivers/mtd/nand/raw/stm32_fmc2_nand.c | 3 +++ > >>> 1 file changed, 3 insertions(+) > >>> > >>> diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c >>> b/drivers/mtd/nand/raw/stm32_fmc2_nand.c > >>> index 5d627048c420..3abb63d00a0b 100644 > >>> --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c > >>> +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c > >>> @@ -1531,6 +1531,9 @@ static int >>> stm32_fmc2_nfc_setup_interface(struct nand_chip *chip, int chipnr, > >>> if (IS_ERR(sdrt)) > >>> return PTR_ERR(sdrt); > >>> + if (sdrt->tRC_min < 30000) > >> > >> When introducing NV-DDR support we as well added a timings.mode field, > >> perhaps you could use it? > > > > Yes, I can use it. It will be done in V2. > > > > Regards, > > Christophe Kerello. > > > > I had a look at Kernel LTS, and timings.mode was introduced on Kernel LTS 5.10. As this patch has also to be applied on Kernel LTS 5.4, my proposal is to send a new patch set. The first patch will be the current patch (fix for all Kernel LTS) and the second patch will use timings.mode instead of checking tRC_min timings for next Kernel delivery. Is this proposal acceptable? Works for me! Thanks, Miquèl
diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c index 5d627048c420..3abb63d00a0b 100644 --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c @@ -1531,6 +1531,9 @@ static int stm32_fmc2_nfc_setup_interface(struct nand_chip *chip, int chipnr, if (IS_ERR(sdrt)) return PTR_ERR(sdrt); + if (sdrt->tRC_min < 30000) + return -EOPNOTSUPP; + if (chipnr == NAND_DATA_IFACE_CHECK_ONLY) return 0;