diff mbox series

[v2,5/6] soc: mediatek: mtk-pmic-wrap: Add support for MT6331 w/ MT6332 companion

Message ID 20230324094205.33266-6-angelogioacchino.delregno@collabora.com
State New
Headers
Series MediaTek Helio X10 MT6795 - MT6331/6332 PMIC Wrapper |

Commit Message

AngeloGioacchino Del Regno March 24, 2023, 9:42 a.m. UTC 
  Add support for the MT6331 PMIC and for its companion MT6332 PMIC.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/soc/mediatek/mtk-pmic-wrap.c | 47 ++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

Comments

Alexandre Mergnat March 29, 2023, 11:17 p.m. UTC | #1 
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>

Regards,
Alexandre

Le ven. 24 mars 2023 à 10:42, AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> a écrit :
>
> Add support for the MT6331 PMIC and for its companion MT6332 PMIC.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  drivers/soc/mediatek/mtk-pmic-wrap.c | 47 ++++++++++++++++++++++++++++
>  1 file changed, 47 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
> index 366e40b802e4..ceeac43f7bd1 100644
> --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
> +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
> @@ -170,6 +170,40 @@ static const u32 mt6323_regs[] = {
>         [PWRAP_DEW_RDDMY_NO] =          0x01a4,
>  };
>
> +static const u32 mt6331_regs[] = {
> +       [PWRAP_DEW_DIO_EN] =            0x018c,
> +       [PWRAP_DEW_READ_TEST] =         0x018e,
> +       [PWRAP_DEW_WRITE_TEST] =        0x0190,
> +       [PWRAP_DEW_CRC_SWRST] =         0x0192,
> +       [PWRAP_DEW_CRC_EN] =            0x0194,
> +       [PWRAP_DEW_CRC_VAL] =           0x0196,
> +       [PWRAP_DEW_MON_GRP_SEL] =       0x0198,
> +       [PWRAP_DEW_CIPHER_KEY_SEL] =    0x019a,
> +       [PWRAP_DEW_CIPHER_IV_SEL] =     0x019c,
> +       [PWRAP_DEW_CIPHER_EN] =         0x019e,
> +       [PWRAP_DEW_CIPHER_RDY] =        0x01a0,
> +       [PWRAP_DEW_CIPHER_MODE] =       0x01a2,
> +       [PWRAP_DEW_CIPHER_SWRST] =      0x01a4,
> +       [PWRAP_DEW_RDDMY_NO] =          0x01a6,
> +};
> +
> +static const u32 mt6332_regs[] = {
> +       [PWRAP_DEW_DIO_EN] =            0x80f6,
> +       [PWRAP_DEW_READ_TEST] =         0x80f8,
> +       [PWRAP_DEW_WRITE_TEST] =        0x80fa,
> +       [PWRAP_DEW_CRC_SWRST] =         0x80fc,
> +       [PWRAP_DEW_CRC_EN] =            0x80fe,
> +       [PWRAP_DEW_CRC_VAL] =           0x8100,
> +       [PWRAP_DEW_MON_GRP_SEL] =       0x8102,
> +       [PWRAP_DEW_CIPHER_KEY_SEL] =    0x8104,
> +       [PWRAP_DEW_CIPHER_IV_SEL] =     0x8106,
> +       [PWRAP_DEW_CIPHER_EN] =         0x8108,
> +       [PWRAP_DEW_CIPHER_RDY] =        0x810a,
> +       [PWRAP_DEW_CIPHER_MODE] =       0x810c,
> +       [PWRAP_DEW_CIPHER_SWRST] =      0x810e,
> +       [PWRAP_DEW_RDDMY_NO] =          0x8110,
> +};
> +
>  static const u32 mt6351_regs[] = {
>         [PWRAP_DEW_DIO_EN] =            0x02F2,
>         [PWRAP_DEW_READ_TEST] =         0x02F4,
> @@ -1182,6 +1216,8 @@ static int mt8186_regs[] = {
>
>  enum pmic_type {
>         PMIC_MT6323,
> +       PMIC_MT6331,
> +       PMIC_MT6332,
>         PMIC_MT6351,
>         PMIC_MT6357,
>         PMIC_MT6358,
> @@ -2041,6 +2077,16 @@ static const struct pwrap_slv_type pmic_mt6323 = {
>                 PWRAP_SLV_CAP_SECURITY,
>  };
>
> +static const struct pwrap_slv_type pmic_mt6331 = {
> +       .dew_regs = mt6331_regs,
> +       .type = PMIC_MT6331,
> +       .comp_dew_regs = mt6332_regs,
> +       .comp_type = PMIC_MT6332,
> +       .regops = &pwrap_regops16,
> +       .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
> +               PWRAP_SLV_CAP_SECURITY,
> +};
> +
>  static const struct pwrap_slv_type pmic_mt6351 = {
>         .dew_regs = mt6351_regs,
>         .type = PMIC_MT6351,
> @@ -2086,6 +2132,7 @@ static const struct pwrap_slv_type pmic_mt6397 = {
>
>  static const struct of_device_id of_slave_match_tbl[] = {
>         { .compatible = "mediatek,mt6323", .data = &pmic_mt6323 },
> +       { .compatible = "mediatek,mt6331", .data = &pmic_mt6331 },
>         { .compatible = "mediatek,mt6351", .data = &pmic_mt6351 },
>         { .compatible = "mediatek,mt6357", .data = &pmic_mt6357 },
>         { .compatible = "mediatek,mt6358", .data = &pmic_mt6358 },
> --
> 2.40.0
>
diff mbox series

Patch

diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
index 366e40b802e4..ceeac43f7bd1 100644
--- a/drivers/soc/mediatek/mtk-pmic-wrap.c
+++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
@@ -170,6 +170,40 @@  static const u32 mt6323_regs[] = {
 	[PWRAP_DEW_RDDMY_NO] =		0x01a4,
 };
 
+static const u32 mt6331_regs[] = {
+	[PWRAP_DEW_DIO_EN] =		0x018c,
+	[PWRAP_DEW_READ_TEST] =		0x018e,
+	[PWRAP_DEW_WRITE_TEST] =	0x0190,
+	[PWRAP_DEW_CRC_SWRST] =		0x0192,
+	[PWRAP_DEW_CRC_EN] =		0x0194,
+	[PWRAP_DEW_CRC_VAL] =		0x0196,
+	[PWRAP_DEW_MON_GRP_SEL] =	0x0198,
+	[PWRAP_DEW_CIPHER_KEY_SEL] =	0x019a,
+	[PWRAP_DEW_CIPHER_IV_SEL] =	0x019c,
+	[PWRAP_DEW_CIPHER_EN] =		0x019e,
+	[PWRAP_DEW_CIPHER_RDY] =	0x01a0,
+	[PWRAP_DEW_CIPHER_MODE] =	0x01a2,
+	[PWRAP_DEW_CIPHER_SWRST] =	0x01a4,
+	[PWRAP_DEW_RDDMY_NO] =		0x01a6,
+};
+
+static const u32 mt6332_regs[] = {
+	[PWRAP_DEW_DIO_EN] =		0x80f6,
+	[PWRAP_DEW_READ_TEST] =		0x80f8,
+	[PWRAP_DEW_WRITE_TEST] =	0x80fa,
+	[PWRAP_DEW_CRC_SWRST] =		0x80fc,
+	[PWRAP_DEW_CRC_EN] =		0x80fe,
+	[PWRAP_DEW_CRC_VAL] =		0x8100,
+	[PWRAP_DEW_MON_GRP_SEL] =	0x8102,
+	[PWRAP_DEW_CIPHER_KEY_SEL] =	0x8104,
+	[PWRAP_DEW_CIPHER_IV_SEL] =	0x8106,
+	[PWRAP_DEW_CIPHER_EN] =		0x8108,
+	[PWRAP_DEW_CIPHER_RDY] =	0x810a,
+	[PWRAP_DEW_CIPHER_MODE] =	0x810c,
+	[PWRAP_DEW_CIPHER_SWRST] =	0x810e,
+	[PWRAP_DEW_RDDMY_NO] =		0x8110,
+};
+
 static const u32 mt6351_regs[] = {
 	[PWRAP_DEW_DIO_EN] =		0x02F2,
 	[PWRAP_DEW_READ_TEST] =		0x02F4,
@@ -1182,6 +1216,8 @@  static int mt8186_regs[] = {
 
 enum pmic_type {
 	PMIC_MT6323,
+	PMIC_MT6331,
+	PMIC_MT6332,
 	PMIC_MT6351,
 	PMIC_MT6357,
 	PMIC_MT6358,
@@ -2041,6 +2077,16 @@  static const struct pwrap_slv_type pmic_mt6323 = {
 		PWRAP_SLV_CAP_SECURITY,
 };
 
+static const struct pwrap_slv_type pmic_mt6331 = {
+	.dew_regs = mt6331_regs,
+	.type = PMIC_MT6331,
+	.comp_dew_regs = mt6332_regs,
+	.comp_type = PMIC_MT6332,
+	.regops = &pwrap_regops16,
+	.caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
+		PWRAP_SLV_CAP_SECURITY,
+};
+
 static const struct pwrap_slv_type pmic_mt6351 = {
 	.dew_regs = mt6351_regs,
 	.type = PMIC_MT6351,
@@ -2086,6 +2132,7 @@  static const struct pwrap_slv_type pmic_mt6397 = {
 
 static const struct of_device_id of_slave_match_tbl[] = {
 	{ .compatible = "mediatek,mt6323", .data = &pmic_mt6323 },
+	{ .compatible = "mediatek,mt6331", .data = &pmic_mt6331 },
 	{ .compatible = "mediatek,mt6351", .data = &pmic_mt6351 },
 	{ .compatible = "mediatek,mt6357", .data = &pmic_mt6357 },
 	{ .compatible = "mediatek,mt6358", .data = &pmic_mt6358 },