From patchwork Fri Mar 24 02:14:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cai Huoqing X-Patchwork-Id: 74309 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp96618wrt; Thu, 23 Mar 2023 19:26:25 -0700 (PDT) X-Google-Smtp-Source: AKy350auxd+VeAMC5oQ7LPCW+X2P8OrYxDb1d29i73ABUQetCVBWEFpPkhKXN3oS92LHFr1aqsuJ X-Received: by 2002:a17:907:98d0:b0:931:2f96:819c with SMTP id kd16-20020a17090798d000b009312f96819cmr944328ejc.27.1679624784825; Thu, 23 Mar 2023 19:26:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1679624784; cv=none; d=google.com; s=arc-20160816; b=OC4oR54YWbRPwnXYqDVAwt4sZsCUuQe7BgQ2jiohWTzp06LeFs9Kc1LiFLUVyY0cS+ neFWPQT0f82u91UJ6qGzwX8HsF9QuSGQz9d2aEvTNQjliaoSJK0hPYY5MbxEcrg8Xpch UcLgseEC2NThCg4PGTse0ujl+FP8bDSJHkINP3K/lQi3f51/lkZ5qNpfoUpGmGN8ZrV3 pV5AvcHEXYLSlIIkoi2gkzmWRgamLZPWd9xliuZ8RSAvLn6IRA6eIO0OMcwdrNjhSuwU 4d3fjNpcjAHWeACjouQchF5vUqz6hccAXU7yQlMts2Ue4tLlOnUIM9Kvw23YTA1Ptdw7 1FRA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=9ZqhxYkuLtJy75J90sFKhndIHhi/agv2yxX2a0SwSLo=; b=Kpk8iDxP9y29afMgasgbteTsfjeQpDpSfDLyp9OzJVKwfm6g8AV1B0LWjaWVNAup0E VTtw7TF72mSyzDr9tFq/HjD27uWqdJsLoKYz7IdWc31paYdB7f1CzF18M/N4jTuSO4c5 oMUgyQpRo6nuMObYIV6HHxmqTaU4QPKE2LULd5EirD+a44ZwzLVRngBJjExGwAgxK/KN p6WWCZ10hrFLhhcJApsQHV+7yhIcjWQqxp+np1HTzAsKLVVXi1JBaugg8ASOff2mzd2o nFB95KWw2SRL/HvQ4HCQePwQP3ARH7Yh4WKoBIHsEGVyczQdqfXFckdjR1bYqKuJUH/f E3mQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linux.dev header.s=key1 header.b=aZyCHdnn; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linux.dev Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id q7-20020a1709064c8700b009220173aa75si5879975eju.456.2023.03.23.19.26.01; Thu, 23 Mar 2023 19:26:24 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linux.dev header.s=key1 header.b=aZyCHdnn; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linux.dev Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231384AbjCXCPQ (ORCPT + 99 others); Thu, 23 Mar 2023 22:15:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229834AbjCXCPM (ORCPT ); Thu, 23 Mar 2023 22:15:12 -0400 Received: from out-28.mta1.migadu.com (out-28.mta1.migadu.com [IPv6:2001:41d0:203:375::1c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 132C3298D5 for ; Thu, 23 Mar 2023 19:14:47 -0700 (PDT) X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1679624085; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9ZqhxYkuLtJy75J90sFKhndIHhi/agv2yxX2a0SwSLo=; b=aZyCHdnnV18mm2Ymycb0I5OSLmNVsneFeRhS4n1qF/1Ulc1UIogw4hv/lUpDx+jU9zxcj5 FoqhdDWIEe45Ftcnv3HXdCuIxnb3QWR7fcRPsCFhEOyIaT/sNVhedUdqnwTXxXb5j7nonr jDP7rgevo91w2yOk5NflpBBEQnHwFJA= From: Cai Huoqing To: fancer.lancer@gmail.com Cc: Cai huoqing , Gustavo Pimentel , Vinod Koul , Jingoo Han , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v9 1/4] dmaengine: dw-edma: Rename dw_edma_core_ops structure to dw_edma_plat_ops Date: Fri, 24 Mar 2023 10:14:15 +0800 Message-Id: <20230324021420.73401-2-cai.huoqing@linux.dev> In-Reply-To: <20230324021420.73401-1-cai.huoqing@linux.dev> References: <20230324021420.73401-1-cai.huoqing@linux.dev> MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761214238317077740?= X-GMAIL-MSGID: =?utf-8?q?1761214238317077740?= From: Cai huoqing The dw_edma_core_ops structure contains a set of the operations: device IRQ numbers getter, CPU/PCI address translation. Based on the functions semantics the structure name "dw_edma_plat_ops" looks more descriptive since indeed the operations are platform-specific. The "dw_edma_core_ops" name shall be used for a structure with the IP-core specific set of callbacks in order to abstract out DW eDMA and DW HDMA setups. Such structure will be added in one of the next commit in the framework of the set of changes adding the DW HDMA device support. Anyway the renaming was necessary to distinguish two types of the implementation callbacks: 1. DW eDMA/hDMA IP-core specific operations: device-specific CSR setups in one or another aspect of the DMA-engine initialization. 2. DW eDMA/hDMA platform specific operations: the DMA device environment configs like IRQs, address translation, etc. Signed-off-by: Cai huoqing Reviewed-by: Serge Semin --- v8->v9: No change v8 link: https://lore.kernel.org/lkml/20230323034944.78357-2-cai.huoqing@linux.dev/ drivers/dma/dw-edma/dw-edma-pcie.c | 4 ++-- drivers/pci/controller/dwc/pcie-designware.c | 2 +- include/linux/dma/edma.h | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c index 2b40f2b44f5e..1c6043751dc9 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -109,7 +109,7 @@ static u64 dw_edma_pcie_address(struct device *dev, phys_addr_t cpu_addr) return region.start; } -static const struct dw_edma_core_ops dw_edma_pcie_core_ops = { +static const struct dw_edma_plat_ops dw_edma_pcie_plat_ops = { .irq_vector = dw_edma_pcie_irq_vector, .pci_address = dw_edma_pcie_address, }; @@ -225,7 +225,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, chip->mf = vsec_data.mf; chip->nr_irqs = nr_irqs; - chip->ops = &dw_edma_pcie_core_ops; + chip->ops = &dw_edma_pcie_plat_ops; chip->ll_wr_cnt = vsec_data.wr_ch_cnt; chip->ll_rd_cnt = vsec_data.rd_ch_cnt; diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 8e33e6e59e68..1f2ee71da4da 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -828,7 +828,7 @@ static int dw_pcie_edma_irq_vector(struct device *dev, unsigned int nr) return platform_get_irq_byname_optional(pdev, name); } -static struct dw_edma_core_ops dw_pcie_edma_ops = { +static struct dw_edma_plat_ops dw_pcie_edma_ops = { .irq_vector = dw_pcie_edma_irq_vector, }; diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h index d2638d9259dc..ed401c965a87 100644 --- a/include/linux/dma/edma.h +++ b/include/linux/dma/edma.h @@ -40,7 +40,7 @@ struct dw_edma_region { * iATU windows. That will be done by the controller * automatically. */ -struct dw_edma_core_ops { +struct dw_edma_plat_ops { int (*irq_vector)(struct device *dev, unsigned int nr); u64 (*pci_address)(struct device *dev, phys_addr_t cpu_addr); }; @@ -80,7 +80,7 @@ enum dw_edma_chip_flags { struct dw_edma_chip { struct device *dev; int nr_irqs; - const struct dw_edma_core_ops *ops; + const struct dw_edma_plat_ops *ops; u32 flags; void __iomem *reg_base;