From patchwork Thu Mar 23 01:56:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Rui" X-Patchwork-Id: 73748 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp2677152wrt; Wed, 22 Mar 2023 19:16:33 -0700 (PDT) X-Google-Smtp-Source: AK7set89HfRIZDRogcM0V46g0qJL8xzvBd4L5lyzwv2oAvq0elE/IYh2V/AM0wmhwo3vFaC28kKw X-Received: by 2002:a05:6a20:7b29:b0:db:9537:2c3 with SMTP id s41-20020a056a207b2900b000db953702c3mr1419286pzh.34.1679537793182; Wed, 22 Mar 2023 19:16:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1679537793; cv=none; d=google.com; s=arc-20160816; b=eSSh7Sx7qjrG38f8nyK9fE/S/QuwJRxKSyDukAH4LqDwxhk7e5j019d9H/pyUYhqDP iGrkfaN+DIhDC3PeNP03LaH3dMuJbJr4tReiZVf8fmckjisunLLyFn1I0cOaJSUrtGN7 jvRFEIGkNpQMweyPn1KnQyNsWwhWWxNsjA2MNRDdBO9N652eujLryThXai/QoXLY/gh2 BAAJOy7S3ExFchwUYRvCBCtQp1EZvZegR0rqT8ZgZnp1KHZRsUajx1rP98v39vM6MF4e nO/hLazXMgsj9U2QD+wMcB9wfQQm9KdZWQwyRIG9r6qDXRpznMSLk+Uj5MGO+clxsAcJ HBcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=H7H0QiywPnagK7dtQQuN8aIp//FyO6vtHML9lfkk7yQ=; b=deq3D/NvmXSxWiw2LFisbOhIBUxQA94LWEgh9wKJsEZiqNWpgFoXnzd/EGR0LbdNon KInivV0rdQVC/5DWEzFFgL3yKhGSY9Nnj7qxBWMThKnt/8+MOyOr+c3FjnyVzDlqG3Mi YFHFrLSUlxZQwp0EWNKXUoFb5mjZStS7BrW6SoiDzKYgq/dr4An7s7FFsZDdEhBB1AuZ Sd4QRpYfZFo9st/B8uXaw+Br6jpHR3gGgL8i5NjPUp41pw2jxh8yBPOm/4lFo9slgwc2 CSx0BCDnNJbJacQXjz+IqdYVRtih+0kxLf8sTCv7R19LeFs8uj4cLhBO2CZrlQ+wEqeD sMfQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=eDsCL6Mj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id q28-20020a635c1c000000b0050bfc85d989si17317659pgb.154.2023.03.22.19.16.19; Wed, 22 Mar 2023 19:16:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=eDsCL6Mj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229996AbjCWB5N (ORCPT + 99 others); Wed, 22 Mar 2023 21:57:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37276 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229642AbjCWB5J (ORCPT ); Wed, 22 Mar 2023 21:57:09 -0400 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24E1D211ED for ; Wed, 22 Mar 2023 18:57:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1679536628; x=1711072628; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=S4J23vlMifTu0C/qcM5GZRfKQJI8Zib/+EwiNhOEfAU=; b=eDsCL6MjRmjnnrXgCSx5YafEprlJrZrAnfhrULGo+YV49iXj04CcfHSG h8dCn7i7SU/XOfzPWYKAou/ky6GdomMRF9m/L73lcCkRLSA7o1K0Hg4kj fYZ5ydwXf59QZtfaonvWAxk6j3xRMozwBKSJWgpKV+RuBmAaZ/VXZiU87 NVkdXwxUjUj/KCqJJZCcdvyY3zNWRnHMlqBaZpJpJ8r4d/R7BpBV7uD7E bMr92JPitl6x5koqgc7RaesPY+f1IETkpqbN0L7WQxn0X3dGuUJ8eyGX2 FLosRKWkJBIz3NVdeGD0dbsJ2l3F6btlUD/fWk7UqWaZp7VNYzeCUwOK8 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="401943931" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="401943931" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Mar 2023 18:57:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="792813180" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="792813180" Received: from jhuan49-mobl1.ccr.corp.intel.com (HELO rzhang1-DESK.intel.com) ([10.255.31.187]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Mar 2023 18:57:03 -0700 From: Zhang Rui To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com Cc: x86@kernel.org, linux-kernel@vger.kernel.org, zhang.jia@linux.alibaba.com, len.brown@intel.com, rui.zhang@intel.com Subject: [PATCH V3] x86/topology: fix erroneous smp_num_siblings on Intel Hybrid platform Date: Thu, 23 Mar 2023 09:56:40 +0800 Message-Id: <20230323015640.27906-1-rui.zhang@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761123021008668221?= X-GMAIL-MSGID: =?utf-8?q?1761123021008668221?= The SMT siblings value returned by CPUID.1F SMT level EBX differs among CPUs on Intel Hybrid platforms like AlderLake and MeteorLake. It returns 2 for Pcore CPUs which have SMT siblings and returns 1 for Ecore CPUs which do not have SMT siblings. Today, the CPU boot code sets the global variable smp_num_siblings when every CPU thread is brought up. The last thread to boot will overwrite it with the number of siblings of *that* thread. That last thread to boot will "win". If the thread is a Pcore, smp_num_siblings == 2. If it is an Ecore, smp_num_siblings == 1. smp_num_siblings describes if the *system* supports SMT. It should specify the maximum number of SMT threads among all cores. Ensure that smp_num_siblings represents the system-wide maximum number of siblings by always increasing its value. Never allow it to decrease. On MeteorLake-P platform, this fixes a problem that the Ecore CPUs are not updated in any cpu sibling map because the system is treated as an UP system when probing Ecore CPUs. Below shows part of the CPU topology information before and after the fix, for both Pcore and Ecore CPU (cpu0 is Pcore, cpu 12 is Ecore). ... -/sys/devices/system/cpu/cpu0/topology/package_cpus:000fff -/sys/devices/system/cpu/cpu0/topology/package_cpus_list:0-11 +/sys/devices/system/cpu/cpu0/topology/package_cpus:3fffff +/sys/devices/system/cpu/cpu0/topology/package_cpus_list:0-21 ... -/sys/devices/system/cpu/cpu12/topology/package_cpus:001000 -/sys/devices/system/cpu/cpu12/topology/package_cpus_list:12 +/sys/devices/system/cpu/cpu12/topology/package_cpus:3fffff +/sys/devices/system/cpu/cpu12/topology/package_cpus_list:0-21 And this also breaks userspace tools like lscpu -Core(s) per socket: 1 -Socket(s): 11 +Core(s) per socket: 16 +Socket(s): 1 CC: stable@kernel.org Fixes: bbb65d2d365e ("x86: use cpuid vector 0xb when available for detecting cpu topology") Fixes: 95f3d39ccf7a ("x86/cpu/topology: Provide detect_extended_topology_early()") Suggested-by: Len Brown Signed-off-by: Zhang Rui Acked-by: Peter Zijlstra (Intel) --- V2 -> V3 Add Acked-by tag from Peter. Add Fixes tag. V1 -> V2 Improve changelog to focus on the smp_num_siblings issue. --- arch/x86/kernel/cpu/topology.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/topology.c b/arch/x86/kernel/cpu/topology.c index 5e868b62a7c4..0270925fe013 100644 --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -79,7 +79,7 @@ int detect_extended_topology_early(struct cpuinfo_x86 *c) * initial apic id, which also represents 32-bit extended x2apic id. */ c->initial_apicid = edx; - smp_num_siblings = LEVEL_MAX_SIBLINGS(ebx); + smp_num_siblings = max_t(int, smp_num_siblings, LEVEL_MAX_SIBLINGS(ebx)); #endif return 0; } @@ -109,7 +109,8 @@ int detect_extended_topology(struct cpuinfo_x86 *c) */ cpuid_count(leaf, SMT_LEVEL, &eax, &ebx, &ecx, &edx); c->initial_apicid = edx; - core_level_siblings = smp_num_siblings = LEVEL_MAX_SIBLINGS(ebx); + core_level_siblings = LEVEL_MAX_SIBLINGS(ebx); + smp_num_siblings = max_t(int, smp_num_siblings, LEVEL_MAX_SIBLINGS(ebx)); core_plus_mask_width = ht_mask_width = BITS_SHIFT_NEXT_LEVEL(eax); die_level_siblings = LEVEL_MAX_SIBLINGS(ebx); pkg_mask_width = die_plus_mask_width = BITS_SHIFT_NEXT_LEVEL(eax);