Message ID | 20230323000657.28664-3-blarson@amd.com |
---|---|
State | New |
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Wed, 22 Mar 2023 19:07:41 -0500 From: Brad Larson <blarson@amd.com> To: <linux-arm-kernel@lists.infradead.org> CC: <linux-kernel@vger.kernel.org>, <linux-mmc@vger.kernel.org>, <linux-spi@vger.kernel.org>, <adrian.hunter@intel.com>, <alcooperx@gmail.com>, <andy.shevchenko@gmail.com>, <arnd@arndb.de>, <blarson@amd.com>, <brendan.higgins@linux.dev>, <briannorris@chromium.org>, <brijeshkumar.singh@amd.com>, <catalin.marinas@arm.com>, <davidgow@google.com>, <gsomlo@gmail.com>, <gerg@linux-m68k.org>, <krzk@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <lee@kernel.org>, <lee.jones@linaro.org>, <broonie@kernel.org>, <yamada.masahiro@socionext.com>, <p.zabel@pengutronix.de>, <piotrs@cadence.com>, <p.yadav@ti.com>, <rdunlap@infradead.org>, <robh+dt@kernel.org>, <samuel@sholland.org>, <fancer.lancer@gmail.com>, <skhan@linuxfoundation.org>, <suravee.suthikulpanit@amd.com>, <thomas.lendacky@amd.com>, <tonyhuang.sunplus@gmail.com>, <ulf.hansson@linaro.org>, <vaishnav.a@ti.com>, <will@kernel.org>, <devicetree@vger.kernel.org> Subject: [PATCH v12 02/15] dt-bindings: mmc: cdns: Add AMD Pensando Elba SoC Date: Wed, 22 Mar 2023 17:06:44 -0700 Message-ID: <20230323000657.28664-3-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230323000657.28664-1-blarson@amd.com> References: <20230323000657.28664-1-blarson@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT021:EE_|DS7PR12MB5885:EE_ X-MS-Office365-Filtering-Correlation-Id: a8dd06c8-52b9-4cfe-2772-08db2b32a092 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Series |
Support AMD Pensando Elba SoC
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Commit Message
Brad Larson
March 23, 2023, 12:06 a.m. UTC
AMD Pensando Elba ARM 64-bit SoC is integrated with this IP and
explicitly controls byte-lane enables.
Signed-off-by: Brad Larson <blarson@amd.com>
---
v12_changes:
- Drop 'resets: false' in the amd,pensando-elba-sd4hc else properties. Passed
dtbs_check and dt_binding_check with both versions.
v11 changes:
- Remove resets description and reset-names
- Add descriptions for amd,pensando-elba-sd4hc reg items
v10 changes:
- Move reset-names property definition next to existing resets prop
- Move allOf to the bottom and set resets/reset-names required only for pensando
- Fix reg maxItems for existing, must be 1
v9 changes:
- Add reset-names and resets properties
- Add if/then on property amd,pensando-elba-sd4hc to set reg property
values for minItems and maxItems
---
.../devicetree/bindings/mmc/cdns,sdhci.yaml | 27 ++++++++++++++++---
1 file changed, 23 insertions(+), 4 deletions(-)
Comments
On 23/03/2023 01:06, Brad Larson wrote: > AMD Pensando Elba ARM 64-bit SoC is integrated with this IP and > explicitly controls byte-lane enables. > > Signed-off-by: Brad Larson <blarson@amd.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml index adacd0535c14..6c40611405a0 100644 --- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml @@ -9,19 +9,18 @@ title: Cadence SD/SDIO/eMMC Host Controller (SD4HC) maintainers: - Masahiro Yamada <yamada.masahiro@socionext.com> -allOf: - - $ref: mmc-controller.yaml - properties: compatible: items: - enum: + - amd,pensando-elba-sd4hc - microchip,mpfs-sd4hc - socionext,uniphier-sd4hc - const: cdns,sd4hc reg: - maxItems: 1 + minItems: 1 + maxItems: 2 interrupts: maxItems: 1 @@ -120,6 +119,26 @@ required: - interrupts - clocks +allOf: + - $ref: mmc-controller.yaml + - if: + properties: + compatible: + contains: + const: amd,pensando-elba-sd4hc + then: + properties: + reg: + items: + - description: Host controller registers + - description: Elba byte-lane enable register for writes + required: + - resets + else: + properties: + reg: + maxItems: 1 + unevaluatedProperties: false examples: