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Wed, 22 Mar 2023 19:09:37 -0500 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v12 10/15] spi: dw: Add support for AMD Pensando Elba SoC Date: Wed, 22 Mar 2023 17:06:52 -0700 Message-ID: <20230323000657.28664-11-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230323000657.28664-1-blarson@amd.com> References: <20230323000657.28664-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000100D3:EE_|IA0PR12MB8647:EE_ X-MS-Office365-Filtering-Correlation-Id: 6404ce8e-3265-46f8-8508-08db2b32e614 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: CV4MTeJz/rPCkS97zsoS7LRSsru/KNI+hugmHdpFSpSbMZOgPgywoVn2Hb4Eq/geejCnSZoEYcCAxA0bjRNCUJnQyV+b0TqugzM7luwneOnVj7mnZ5RB6K2i4NCXqOLqIhBWI4Ly/jMAzW1EQ9ivOt4Vof1RB2F6ImjRTp6yGh5dIwhtSQVULO+ynumQKKBtXQQDtbQwjojfKGu6jTDVdVWCQqstGPARrhxCzgs0saeFuvGkr9mJ7uQxeSEKbN0ZTX7w/I9VkcfQNYTsq+XhCJsnCRSVip8RHbe+pXSiA3BWLimG7b2mkJ4u+1gPQHwkitvGbJy3IpJrpYjp4iPu2J+CAtI7RUY2jJrN2eOyDiBYMHBHua1nO+LBebPd1Cule49EIqp0oF8H/5BVT535Dj3jeqVRTocRsfv7+jqsYfqW2lGC2gr3WFMu2xnxwn+Em8ta3vzziJPx8GDfhey1WrNDj9LVtO/r9R6lQiUmzqZWURwTOYFhv9qq/pHM1BCG+B6qfi6fqgzsj0pXJyPjBsvVat0kmZ3r6CTPgY7LY2L6+mbZwOQBf0VfV1AGtgc6M+tvLcYBYWYyAH1Fl03qLZVOGfWOUbaRckhAVGfNUEkOvKZhUBAbCULogJ/nGNzAMFjah/Lyhr/p3K6Ixoht3euRyXrYM0PUY2igpEPCHssE5pnvGhDwFPGgaMreiUs6EZ8WMEuiEFPZ4hfMVmIkEuFre6NIPNmfYbMxga741LA= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(376002)(136003)(396003)(39860400002)(346002)(451199018)(36840700001)(40470700004)(46966006)(82310400005)(82740400003)(2616005)(16526019)(1076003)(26005)(6666004)(36756003)(336012)(7406005)(2906002)(7416002)(356005)(47076005)(426003)(81166007)(5660300002)(8936002)(36860700001)(41300700001)(40460700003)(83380400001)(478600001)(40480700001)(54906003)(186003)(6916009)(70586007)(316002)(8676002)(4326008)(70206006)(36900700001);DIR:OUT;SFP:1101; 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The Elba SoC provides four chip-selects where the native DW IP supports two chip-selects. The Elba DW_SPI instance has two native CS signals that are always overridden. Signed-off-by: Brad Larson Reviewed-by: Serge Semin --- v12 changes: - Add a newline in function dw_spi_elba_init() v11 changes: - Simplify dw_spi_elb_init by using syscon_regmap_lookup_by_phandle() v10 changes: - Delete struct dw_spi_elba, use regmap directly in priv v9 changes: - Add use of macros GENMASK() and BIT() - Change ELBA_SPICS_SHIFT() to ELBA_SPICS_OFFSET() --- drivers/spi/spi-dw-mmio.c | 58 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index 26c40ea6dd12..8cfad64b5463 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -53,6 +53,20 @@ struct dw_spi_mscc { void __iomem *spi_mst; /* Not sparx5 */ }; +/* + * Elba SoC does not use ssi, pin override is used for cs 0,1 and + * gpios for cs 2,3 as defined in the device tree. + * + * cs: | 1 0 + * bit: |---3-------2-------1-------0 + * | cs1 cs1_ovr cs0 cs0_ovr + */ +#define ELBA_SPICS_REG 0x2468 +#define ELBA_SPICS_OFFSET(cs) ((cs) << 1) +#define ELBA_SPICS_MASK(cs) (GENMASK(1, 0) << ELBA_SPICS_OFFSET(cs)) +#define ELBA_SPICS_SET(cs, val) \ + ((((val) << 1) | BIT(0)) << ELBA_SPICS_OFFSET(cs)) + /* * The Designware SPI controller (referred to as master in the documentation) * automatically deasserts chip select when the tx fifo is empty. The chip @@ -237,6 +251,49 @@ static int dw_spi_canaan_k210_init(struct platform_device *pdev, return 0; } +static void dw_spi_elba_override_cs(struct regmap *syscon, int cs, int enable) +{ + regmap_update_bits(syscon, ELBA_SPICS_REG, ELBA_SPICS_MASK(cs), + ELBA_SPICS_SET(cs, enable)); +} + +static void dw_spi_elba_set_cs(struct spi_device *spi, bool enable) +{ + struct dw_spi *dws = spi_master_get_devdata(spi->master); + struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws); + struct regmap *syscon = dwsmmio->priv; + u8 cs; + + cs = spi->chip_select; + if (cs < 2) + dw_spi_elba_override_cs(syscon, spi->chip_select, enable); + + /* + * The DW SPI controller needs a native CS bit selected to start + * the serial engine. + */ + spi->chip_select = 0; + dw_spi_set_cs(spi, enable); + spi->chip_select = cs; +} + +static int dw_spi_elba_init(struct platform_device *pdev, + struct dw_spi_mmio *dwsmmio) +{ + struct regmap *syscon; + + syscon = syscon_regmap_lookup_by_phandle(dev_of_node(&pdev->dev), + "amd,pensando-elba-syscon"); + if (IS_ERR(syscon)) + return dev_err_probe(&pdev->dev, PTR_ERR(syscon), + "syscon regmap lookup failed\n"); + + dwsmmio->priv = syscon; + dwsmmio->dws.set_cs = dw_spi_elba_set_cs; + + return 0; +} + static int dw_spi_mmio_probe(struct platform_device *pdev) { int (*init_func)(struct platform_device *pdev, @@ -352,6 +409,7 @@ static const struct of_device_id dw_spi_mmio_of_match[] = { { .compatible = "intel,thunderbay-ssi", .data = dw_spi_intel_init}, { .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init}, { .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init}, + { .compatible = "amd,pensando-elba-spi", .data = dw_spi_elba_init}, { /* end of table */} }; MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);