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Wed, 22 Mar 2023 19:09:19 -0500 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v12 09/15] spi: cadence-quadspi: Add compatible for AMD Pensando Elba SoC Date: Wed, 22 Mar 2023 17:06:51 -0700 Message-ID: <20230323000657.28664-10-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230323000657.28664-1-blarson@amd.com> References: <20230323000657.28664-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000100D1:EE_|SA1PR12MB8144:EE_ X-MS-Office365-Filtering-Correlation-Id: 3fe823b9-70b1-4af7-8352-08db2b32dad0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: BNj/wH4N1SA9MJXhSqx4GO9TS5rO3yaeekqIxVFMhXbn89BtB0qAtLGrSLAN17Z9mrzo63/iwujkHPk09e3Z5JcizvCEGk1vpdDhYsw/bzeoaQi6XYtGOlkF5eWv2sdLViX0ifqQzxrO2ZbEx1tdq2xkIWxp4InElLh/0Y3t9j46AQ24calq5S/CIZ+WEZ0nWtlT327qhv/gqgH0OMeZEQqY6fStUZkhbAwSPauqGMLBlHlMxIvi3DWrXkND12jNv9/ZLZi8yhjEiYTIDWw0T48plcDbkN3vNIJqNWJF91vwLa2g3c9eJBjAipbhJ8s5mwoYJz7gVQhaTWbJOL5ryBYpaB/Bs2PZcTzvprSWM7kSUb9/zVtjc9Pz4XGvj+fPvDo29KQD+7B1rLLWKimw6Lq+5XXDmiS2jdFyWk8f0e2gSPwLJCKlPS1+2VPWUiMymLgjg/lgJEk+wXwHUl2RTKgVlcaL6ytNdF9iI2gCZLErpMOqSOx0irYoEYN6mq+IysoHnmEp1xQl4hk8wEdpkI1C4aCs+vtJNKrqQtDULKBFcB/dzKaV54xNvCzRztMWirUiIhrwT66WrAGl42q7piba64iJOpgA7116XL5pQlASfT7WSATSKuYWpNOPisOYPslx68BXoPRaoOZUCl5+KqBPSbjCsYfQcie//HjEDjT7fqdL1uvMeuKN4DdjsQH9efTx+soIFYLsKo8qCBYatoOWd4JUPZ3G/7EzOnJICdY= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(396003)(346002)(376002)(39860400002)(136003)(451199018)(36840700001)(40470700004)(46966006)(8936002)(336012)(36756003)(7416002)(40460700003)(7406005)(5660300002)(40480700001)(426003)(47076005)(36860700001)(2616005)(2906002)(82310400005)(478600001)(316002)(54906003)(81166007)(41300700001)(82740400003)(4326008)(1076003)(26005)(8676002)(6916009)(70586007)(356005)(6666004)(186003)(16526019)(70206006)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2023 00:09:22.1108 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3fe823b9-70b1-4af7-8352-08db2b32dad0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000100D1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8144 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761116399434392897?= X-GMAIL-MSGID: =?utf-8?q?1761116399434392897?= The AMD Pensando Elba SoC has the Cadence QSPI controller integrated. The quirk CQSPI_NEEDS_APB_AHB_HAZARD_WAR is added and if enabled a dummy readback from the controller is performed to ensure synchronization. Signed-off-by: Brad Larson --- v9 changes: - Rebase to linux-next 6.2.0-rc1 --- drivers/spi/spi-cadence-quadspi.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 64b6a460d739..ad82d2ab3442 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -40,6 +40,7 @@ #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) #define CQSPI_SLOW_SRAM BIT(4) +#define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5) /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) @@ -90,6 +91,7 @@ struct cqspi_st { u32 pd_dev_id; bool wr_completion; bool slow_sram; + bool apb_ahb_hazard; }; struct cqspi_driver_platdata { @@ -1004,6 +1006,13 @@ static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, if (cqspi->wr_delay) ndelay(cqspi->wr_delay); + /* + * If a hazard exists between the APB and AHB interfaces, perform a + * dummy readback from the controller to ensure synchronization. + */ + if (cqspi->apb_ahb_hazard) + readl(reg_base + CQSPI_REG_INDIRECTWR); + while (remaining > 0) { size_t write_words, mod_bytes; @@ -1734,6 +1743,8 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->wr_completion = false; if (ddata->quirks & CQSPI_SLOW_SRAM) cqspi->slow_sram = true; + if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) + cqspi->apb_ahb_hazard = true; if (of_device_is_compatible(pdev->dev.of_node, "xlnx,versal-ospi-1.0")) @@ -1859,6 +1870,10 @@ static const struct cqspi_driver_platdata versal_ospi = { .get_dma_status = cqspi_get_versal_dma_status, }; +static const struct cqspi_driver_platdata pensando_cdns_qspi = { + .quirks = CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE, +}; + static const struct of_device_id cqspi_dt_ids[] = { { .compatible = "cdns,qspi-nor", @@ -1884,6 +1899,10 @@ static const struct of_device_id cqspi_dt_ids[] = { .compatible = "intel,socfpga-qspi", .data = &socfpga_qspi, }, + { + .compatible = "amd,pensando-elba-qspi", + .data = &pensando_cdns_qspi, + }, { /* end of table */ } };