[v7,8/9] dt-bindings: clock: Add Hi3798MV100 CRG
Commit Message
Add CRG bindings for Hi3798MV100 SoC. CRG (Clock and Reset Generator)
module generates clock and reset signals used by other module blocks on
SoC.
Signed-off-by: David Yang <mmyangfl@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../devicetree/bindings/clock/hisi-crg.txt | 2 ++
include/dt-bindings/clock/histb-clock.h | 13 +++++++++++++
2 files changed, 15 insertions(+)
@@ -13,6 +13,8 @@ Required Properties:
- "hisilicon,hi3516cv300-crg"
- "hisilicon,hi3516cv300-sysctrl"
- "hisilicon,hi3519-crg"
+ - "hisilicon,hi3798mv100-crg"
+ - "hisilicon,hi3798mv100-sysctrl"
- "hisilicon,hi3798cv200-crg"
- "hisilicon,hi3798cv200-sysctrl"
@@ -58,6 +58,19 @@
#define HISTB_USB3_UTMI_CLK1 48
#define HISTB_USB3_PIPE_CLK1 49
#define HISTB_USB3_SUSPEND_CLK1 50
+#define HISTB_USB2_UTMI_CLK1 51
+#define HISTB_USB2_2_BUS_CLK 52
+#define HISTB_USB2_2_PHY_CLK 53
+#define HISTB_USB2_2_UTMI_CLK 54
+#define HISTB_USB2_2_UTMI_CLK1 55
+#define HISTB_USB2_2_12M_CLK 56
+#define HISTB_USB2_2_48M_CLK 57
+#define HISTB_USB2_2_OTG_UTMI_CLK 58
+#define HISTB_USB2_2_PHY1_REF_CLK 59
+#define HISTB_USB2_2_PHY2_REF_CLK 60
+#define HISTB_FEPHY_CLK 61
+#define HISTB_GPU_BUS_CLK 62
+#define HISTB_GPU_CORE_CLK 63
/* clocks provided by mcu CRG */
#define HISTB_MCE_CLK 1