Message ID | 20230322032202.12598-2-shawn.sung@mediatek.com |
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State | New |
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[2620:137:e000::1:20]) by mx.google.com with ESMTP id pv7-20020a170907208700b009314f2c4e80si10496719ejb.873.2023.03.21.20.31.37; Tue, 21 Mar 2023 20:32:00 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=q7bK7iGs; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230175AbjCVDXB (ORCPT <rfc822;ezelljr.billy@gmail.com> + 99 others); Tue, 21 Mar 2023 23:23:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229838AbjCVDWy (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Tue, 21 Mar 2023 23:22:54 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 725615652D; Tue, 21 Mar 2023 20:22:49 -0700 (PDT) X-UUID: ce1da9a2c86011edb6b9f13eb10bd0fe-20230322 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=RSPxWcIg1Osvz8bIovKM5keV/3d/k1WnFlYzKJH8ckM=; b=q7bK7iGsM5dGmF0a+mA1l6kfeRKnMePKyUKJzWoUXF5B5OeTBbP2MuDQGHmUa9tn/B7MZdUyOUGkRNlsqbiDyevR+/ECebSMhwk37K0+ZXiepbNeALV68E6GqE7+Iq5hZI2fs+yrJ3IrP90BIWoGOX5M0xp6NGzgKYAYbQ/25Ps=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.22,REQID:bf1d1bea-d929-4835-910b-1cb3658f5da1,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:100,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:100 X-CID-INFO: VERSION:1.1.22,REQID:bf1d1bea-d929-4835-910b-1cb3658f5da1,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:100,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:100 X-CID-META: VersionHash:120426c,CLOUDID:902cf9b3-beed-4dfc-bd9c-e1b22fa6ccc4,B ulkID:230322112243BQPGG959,BulkQuantity:1,Recheck:0,SF:38|29|28|17|19|48,T C:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:43,QS:nil,BEC:nil,COL:0, OSI:0,OSA:0,AV:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-UUID: ce1da9a2c86011edb6b9f13eb10bd0fe-20230322 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from <shawn.sung@mediatek.com>) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 140167419; Wed, 22 Mar 2023 11:22:41 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Wed, 22 Mar 2023 11:22:40 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Wed, 22 Mar 2023 11:22:40 +0800 From: Shawn Sung <shawn.sung@mediatek.com> To: Matthias Brugger <matthias.bgg@gmail.com>, AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>, Philipp Zabel <p.zabel@pengutronix.de>, Rob Herring <robh+dt@kernel.org>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org> CC: <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-mediatek@lists.infradead.org>, <devicetree@vger.kernel.org>, <Project_Global_Chrome_Upstream_Group@mediatek.com>, Chun-Kuang Hu <chunkuang.hu@kernel.org>, Singo Chang <singo.chang@mediatek.com>, Nancy Lin <nancy.lin@mediatek.com>, Jason-JH Lin <jason-jh.lin@mediatek.com>, "Shawn Sung" <shawn.sung@mediatek.com> Subject: [PATCH v1 1/2] dt-bindings: reset: mt8188: Add reset control for DSI0 Date: Wed, 22 Mar 2023 11:22:01 +0800 Message-ID: <20230322032202.12598-2-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230322032202.12598-1-shawn.sung@mediatek.com> References: <20230322032202.12598-1-shawn.sung@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, T_SPF_TEMPERROR,UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761037171937314686?= X-GMAIL-MSGID: =?utf-8?q?1761037171937314686?= |
Series |
Add reset control for DSI0
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Commit Message
Shawn Sung (宋孝謙)
March 22, 2023, 3:22 a.m. UTC
Add reset control for DSI0.
Signed-off-by: Shawn Sung <shawn.sung@mediatek.com>
---
include/dt-bindings/reset/mt8188-resets.h | 3 +++
1 file changed, 3 insertions(+)
--
2.18.0
Comments
On 22/03/2023 04:22, Shawn Sung wrote: > Add reset control for DSI0. > > Signed-off-by: Shawn Sung <shawn.sung@mediatek.com> > --- > include/dt-bindings/reset/mt8188-resets.h | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h > index 377cdfda82a9..5c9e74130ef0 100644 > --- a/include/dt-bindings/reset/mt8188-resets.h > +++ b/include/dt-bindings/reset/mt8188-resets.h > @@ -33,4 +33,7 @@ > > #define MT8188_TOPRGU_SW_RST_NUM 24 > > +/* VDOSYS0 */ > +#define MT8188_VDO0_RST_DSI0 21 Why this is not 0? IDs start from 0. Best regards, Krzysztof
Il 22/03/23 09:34, Krzysztof Kozlowski ha scritto: > On 22/03/2023 04:22, Shawn Sung wrote: >> Add reset control for DSI0. >> >> Signed-off-by: Shawn Sung <shawn.sung@mediatek.com> >> --- >> include/dt-bindings/reset/mt8188-resets.h | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h >> index 377cdfda82a9..5c9e74130ef0 100644 >> --- a/include/dt-bindings/reset/mt8188-resets.h >> +++ b/include/dt-bindings/reset/mt8188-resets.h >> @@ -33,4 +33,7 @@ >> >> #define MT8188_TOPRGU_SW_RST_NUM 24 >> >> +/* VDOSYS0 */ >> +#define MT8188_VDO0_RST_DSI0 21 > > Why this is not 0? IDs start from 0. > Because mtk-mmsys needs to be fixed, bindings IDs are *again* 1:1 with HW bits, there's no mapping like the one that was "recently" done in clk/mediatek resets. Since VDO0/1 have got lots of holes in reset bit mapping, it's definitely time to fix this situation now..... Shawn, please fix. For your reference, look at [1] and [2]. [1]: https://lore.kernel.org/all/20220523060056.24396-9-rex-bc.chen@mediatek.com/ [2]: https://lore.kernel.org/all/20220523060056.24396-15-rex-bc.chen@mediatek.com/ Regards, Angelo >
diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h index 377cdfda82a9..5c9e74130ef0 100644 --- a/include/dt-bindings/reset/mt8188-resets.h +++ b/include/dt-bindings/reset/mt8188-resets.h @@ -33,4 +33,7 @@ #define MT8188_TOPRGU_SW_RST_NUM 24 +/* VDOSYS0 */ +#define MT8188_VDO0_RST_DSI0 21 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */