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[2620:137:e000::1:20]) by mx.google.com with ESMTP id v10-20020a170902b7ca00b0019b0b007981si13233071plz.531.2023.03.21.13.12.44; Tue, 21 Mar 2023 13:12:57 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20210112 header.b=PZJRTsm9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230083AbjCUUCW (ORCPT + 99 others); Tue, 21 Mar 2023 16:02:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37990 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230044AbjCUUCU (ORCPT ); Tue, 21 Mar 2023 16:02:20 -0400 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 098DA53712; Tue, 21 Mar 2023 13:01:48 -0700 (PDT) Received: by mail-pl1-x636.google.com with SMTP id o11so17261204ple.1; Tue, 21 Mar 2023 13:01:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679428902; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8phvAVZ6WLP5gFAw+M761A2GnXN7k1pWxMfd/tGnvds=; b=PZJRTsm92ozFzAei+hay/FfSkwTCCSAUQJBsS9oQEhNAxtuJZ9LBeSC+u+HyKsd13g qIEPmTZpqYJ4Mq8HOwCIOK8thNiHQ7W9oRq8KokcB9OH5uWUZvQ3KGL/Txay9KNCjP3N y3MOKRhL5sVLPz0n3G/kF4xAZFtvmtQTU4/OSID0bMCyncxevwpa+hDFZ7Iatm+KmhoV oCp23FElAmgoBDEUCgzbqhOV9HVClM9mRV3CnReTbKaU3Y11BnXKxumQJ63yxXXh4jsl cQWMzvNesLWu5lXT9rqB4fBNjLeddcJItrQ2fmFtJKeGarZjkxLcZFYu1jifk6pMR+ib Byvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679428902; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8phvAVZ6WLP5gFAw+M761A2GnXN7k1pWxMfd/tGnvds=; b=JhivQo7YwqOyYLsDKU6Wms7/6qGJbnTXG+fcxnOoHtivt/pkYgonrvzfs23R4K1sdM fL+Zme9dzZ0VUObAOmuSQ8p/mqALRSj08aCKZgzx8eFVnVS0eiSFP54peAUkdnps+2sr W1BIzZNyi9DzXXRUerRqjpCzQ8X3cFgOsZZ5EMtTA/HZ8BJnIFJD6KHcRN5j30gX/LdF R2V/9S8NB/K4wS48ufGNlG/MjVS8wP760Kvg4969tbrdoLLV4ROD0JHi2OfUV53V+H7F GSqUU431VndFtx75lbVsVEX30fF/18d9WBFJg5xTFa/1/c/ANowtg/wLg2bTTy7jYxeZ CV8Q== X-Gm-Message-State: AO0yUKWVn/FQ7G0Y97Nod/fjZTO0Wn34GlNom4yzj6C2c7elDf+pk2t3 jtnE5l3T8EknAIo2QFyU88U= X-Received: by 2002:a17:90b:38cf:b0:23d:2027:c355 with SMTP id nn15-20020a17090b38cf00b0023d2027c355mr1122058pjb.10.1679428902504; Tue, 21 Mar 2023 13:01:42 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.245.199]) by smtp.gmail.com with ESMTPSA id mt19-20020a17090b231300b0023b5528b8d4sm930557pjb.19.2023.03.21.13.01.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Mar 2023 13:01:42 -0700 (PDT) From: David Yang Cc: David Yang , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 6/6] clk: hisilicon: Add CRG driver for Hi3798MV100 SoC Date: Wed, 22 Mar 2023 04:00:27 +0800 Message-Id: <20230321200031.1812026-7-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230321200031.1812026-1-mmyangfl@gmail.com> References: <20230321200031.1812026-1-mmyangfl@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761009548828750598?= X-GMAIL-MSGID: =?utf-8?q?1761009548828750598?= Add CRG driver for Hi3798MV100 SoC. CRG (Clock and Reset Generator) module generates clock and reset signals used by other module blocks on SoC. Signed-off-by: David Yang --- drivers/clk/hisilicon/crg-hi3798.c | 191 ++++++++++++++++++++++++++--- 1 file changed, 175 insertions(+), 16 deletions(-) diff --git a/drivers/clk/hisilicon/crg-hi3798.c b/drivers/clk/hisilicon/crg-hi3798.c index 78915bd26..34f92f492 100644 --- a/drivers/clk/hisilicon/crg-hi3798.c +++ b/drivers/clk/hisilicon/crg-hi3798.c @@ -42,6 +42,9 @@ #define HI3798_FIXED_166P5M 84 #define HI3798_SDIO0_MUX 85 #define HI3798_COMBPHY0_MUX 86 +#define HI3798_FIXED_3M 87 +#define HI3798_FIXED_15M 88 +#define HI3798_FIXED_83P3M 89 #define HI3798_CRG_NR_CLKS 128 @@ -49,13 +52,16 @@ static const struct hisi_fixed_rate_clock hi3798_fixed_rate_clks[] = { { HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, }, { HISTB_APB_CLK, "clk_apb", NULL, 0, 100000000, }, { HISTB_AHB_CLK, "clk_ahb", NULL, 0, 200000000, }, + { HI3798_FIXED_3M, "3m", NULL, 0, 3000000, }, { HI3798_FIXED_12M, "12m", NULL, 0, 12000000, }, + { HI3798_FIXED_15M, "15m", NULL, 0, 15000000, }, { HI3798_FIXED_24M, "24m", NULL, 0, 24000000, }, { HI3798_FIXED_25M, "25m", NULL, 0, 25000000, }, { HI3798_FIXED_48M, "48m", NULL, 0, 48000000, }, { HI3798_FIXED_50M, "50m", NULL, 0, 50000000, }, { HI3798_FIXED_60M, "60m", NULL, 0, 60000000, }, { HI3798_FIXED_75M, "75m", NULL, 0, 75000000, }, + { HI3798_FIXED_83P3M, "83p3m", NULL, 0, 83333333, }, { HI3798_FIXED_100M, "100m", NULL, 0, 100000000, }, { HI3798_FIXED_150M, "150m", NULL, 0, 150000000, }, { HI3798_FIXED_166P5M, "166p5m", NULL, 0, 165000000, }, @@ -71,7 +77,6 @@ struct hi3798_complex_clock { unsigned long offset; u32 mask; u32 value; - const char *alias; }; struct hi3798_clk_complex { @@ -157,27 +162,12 @@ static int hi3798_clk_register_complex(struct device *dev, return ret; } - if (clks[i].alias) - clk_register_clkdev(clk, clks[i].alias, NULL); - data->clk_data->hws[clks[i].id] = &p_clk->hw; } return 0; } -static void hi3798_clk_unregister_complex(const struct hi3798_complex_clock *clks, int nums, - struct hisi_clock_data *data) -{ - struct clk **clocks = data->clk_data.clks; - int i; - - for (i = 0; i < nums; i++) { - if (clocks[clks[i].id]) - clk_unregister(clocks[clks[i].id]); - } -} - struct hi3798_clks { const struct hisi_gate_clock *gate_clks; int gate_clks_nums; @@ -464,11 +454,180 @@ static const struct hisi_crg_funcs hi3798cv200_sysctrl_funcs = { .unregister_clks = hi3798cv200_sysctrl_clk_unregister, }; +/* hi3798MV100 */ + +static const char *const hi3798mv100_mmc_mux_p[] = { + "75m", "100m", "50m", "15m" }; +static u32 hi3798mv100_mmc_mux_table[] = {0, 1, 2, 3}; + +static struct hisi_mux_clock hi3798mv100_mux_clks[] = { + { HI3798_MMC_MUX, "mmc_mux", hi3798mv100_mmc_mux_p, + ARRAY_SIZE(hi3798mv100_mmc_mux_p), CLK_SET_RATE_PARENT, + 0xa0, 8, 2, 0, hi3798mv100_mmc_mux_table, }, + { HI3798_SDIO0_MUX, "sdio0_mux", hi3798mv100_mmc_mux_p, + ARRAY_SIZE(hi3798mv100_mmc_mux_p), CLK_SET_RATE_PARENT, + 0x9c, 8, 2, 0, hi3798mv100_mmc_mux_table, }, +}; + +static const struct hisi_gate_clock hi3798mv100_gate_clks[] = { + /* NAND */ + /* hi3798MV100 NAND driver does not get into mainline yet, + * expose these clocks when it gets ready */ + /* { HISTB_NAND_CLK, "clk_nand", "clk_apb", + CLK_SET_RATE_PARENT, 0x60, 0, 0, }, */ + /* UART */ + { HISTB_UART1_CLK, "clk_uart1", "3m", + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0x68, 0, 0, }, + { HISTB_UART2_CLK, "clk_uart2", "83p3m", + CLK_SET_RATE_PARENT, 0x68, 4, 0, }, + /* I2C */ + { HISTB_I2C0_CLK, "clk_i2c0", "clk_apb", + CLK_SET_RATE_PARENT, 0x6C, 4, 0, }, + { HISTB_I2C1_CLK, "clk_i2c1", "clk_apb", + CLK_SET_RATE_PARENT, 0x6C, 8, 0, }, + { HISTB_I2C2_CLK, "clk_i2c2", "clk_apb", + CLK_SET_RATE_PARENT, 0x6C, 12, 0, }, + /* SPI */ + { HISTB_SPI0_CLK, "clk_spi0", "clk_apb", + CLK_SET_RATE_PARENT, 0x70, 0, 0, }, + /* SDIO */ + { HISTB_SDIO0_BIU_CLK, "clk_sdio0_biu", "200m", + CLK_SET_RATE_PARENT, 0x9c, 0, 0, }, + { HISTB_SDIO0_CIU_CLK, "clk_sdio0_ciu", "sdio0_mux", + CLK_SET_RATE_PARENT, 0x9c, 1, 0, }, + /* EMMC */ + { HISTB_MMC_BIU_CLK, "clk_mmc_biu", "200m", + CLK_SET_RATE_PARENT, 0xa0, 0, 0, }, + { HISTB_MMC_CIU_CLK, "clk_mmc_ciu", "mmc_mux", + CLK_SET_RATE_PARENT, 0xa0, 1, 0, }, + /* USB2 */ + { HISTB_USB2_BUS_CLK, "clk_u2_bus", "clk_ahb", + CLK_SET_RATE_PARENT, 0xb8, 0, 0, }, + { HISTB_USB2_PHY_CLK, "clk_u2_phy", "60m", + CLK_SET_RATE_PARENT, 0xb8, 4, 0, }, + { HISTB_USB2_12M_CLK, "clk_u2_12m", "12m", + CLK_SET_RATE_PARENT, 0xb8, 2, 0 }, + { HISTB_USB2_48M_CLK, "clk_u2_48m", "48m", + CLK_SET_RATE_PARENT, 0xb8, 1, 0 }, + { HISTB_USB2_UTMI_CLK, "clk_u2_utmi", "60m", + CLK_SET_RATE_PARENT, 0xb8, 5, 0 }, + { HISTB_USB2_UTMI_CLK1, "clk_u2_utmi1", "60m", + CLK_SET_RATE_PARENT, 0xb8, 6, 0 }, + { HISTB_USB2_OTG_UTMI_CLK, "clk_u2_otg_utmi", "60m", + CLK_SET_RATE_PARENT, 0xb8, 3, 0 }, + { HISTB_USB2_PHY1_REF_CLK, "clk_u2_phy1_ref", "24m", + CLK_SET_RATE_PARENT, 0xbc, 0, 0 }, + { HISTB_USB2_PHY2_REF_CLK, "clk_u2_phy2_ref", "24m", + CLK_SET_RATE_PARENT, 0xbc, 2, 0 }, + /* USB2 2 */ + { HISTB_USB2_2_BUS_CLK, "clk_u2_2_bus", "clk_ahb", + CLK_SET_RATE_PARENT, 0x198, 0, 0, }, + { HISTB_USB2_2_PHY_CLK, "clk_u2_2_phy", "60m", + CLK_SET_RATE_PARENT, 0x198, 4, 0, }, + { HISTB_USB2_2_12M_CLK, "clk_u2_2_12m", "12m", + CLK_SET_RATE_PARENT, 0x198, 2, 0 }, + { HISTB_USB2_2_48M_CLK, "clk_u2_2_48m", "48m", + CLK_SET_RATE_PARENT, 0x198, 1, 0 }, + { HISTB_USB2_2_UTMI_CLK, "clk_u2_2_utmi", "60m", + CLK_SET_RATE_PARENT, 0x198, 5, 0 }, + { HISTB_USB2_2_UTMI_CLK1, "clk_u2_2_utmi1", "60m", + CLK_SET_RATE_PARENT, 0x198, 6, 0 }, + { HISTB_USB2_2_OTG_UTMI_CLK, "clk_u2_2_otg_utmi", "60m", + CLK_SET_RATE_PARENT, 0x198, 3, 0 }, + { HISTB_USB2_2_PHY1_REF_CLK, "clk_u2_2_phy1_ref", "24m", + CLK_SET_RATE_PARENT, 0x190, 0, 0 }, + { HISTB_USB2_2_PHY2_REF_CLK, "clk_u2_2_phy2_ref", "24m", + CLK_SET_RATE_PARENT, 0x190, 2, 0 }, + /* USB3 */ + { HISTB_USB3_BUS_CLK, "clk_u3_bus", NULL, + CLK_SET_RATE_PARENT, 0xb0, 0, 0 }, + { HISTB_USB3_UTMI_CLK, "clk_u3_utmi", NULL, + CLK_SET_RATE_PARENT, 0xb0, 4, 0 }, + { HISTB_USB3_PIPE_CLK, "clk_u3_pipe", NULL, + CLK_SET_RATE_PARENT, 0xb0, 3, 0 }, + { HISTB_USB3_SUSPEND_CLK, "clk_u3_suspend", NULL, + CLK_SET_RATE_PARENT, 0xb0, 2, 0 }, + /* GPU */ + { HISTB_GPU_BUS_CLK, "clk_gpu", "200m", + CLK_SET_RATE_PARENT, 0xd4, 0, 0 }, + /* FEPHY */ + { HISTB_FEPHY_CLK, "clk_fephy", "25m", + CLK_SET_RATE_PARENT, 0x120, 0, 0, }, +}; + +static const struct hi3798_complex_clock hi3798mv100_complex_clks[] = { + { HISTB_ETH0_MAC_CLK, "clk_mac0", NULL, + CLK_SET_RATE_PARENT, 0xcc, 0xf, 0xb, }, + { HISTB_GPU_CORE_CLK, "clk_gpu_gp", "200m", + CLK_SET_RATE_PARENT, 0xd4, 0x700, 0x700, }, +}; + +static const struct hi3798_clks hi3798mv100_crg_clks = { + .gate_clks = hi3798mv100_gate_clks, + .gate_clks_nums = ARRAY_SIZE(hi3798mv100_gate_clks), + .mux_clks = hi3798mv100_mux_clks, + .mux_clks_nums = ARRAY_SIZE(hi3798mv100_mux_clks), + .phase_clks = hi3798cv200_phase_clks, + .phase_clks_nums = ARRAY_SIZE(hi3798cv200_phase_clks), + .complex_clks = hi3798mv100_complex_clks, + .complex_clks_nums = ARRAY_SIZE(hi3798mv100_complex_clks), +}; + +static struct hisi_clock_data *hi3798mv100_clk_register( + struct platform_device *pdev) +{ + return hi3798_clk_register(pdev, &hi3798mv100_crg_clks); +} + +static void hi3798mv100_clk_unregister(struct platform_device *pdev) +{ + hi3798_clk_unregister(pdev, &hi3798mv100_crg_clks); +} + +static const struct hisi_crg_funcs hi3798mv100_crg_funcs = { + .register_clks = hi3798mv100_clk_register, + .unregister_clks = hi3798mv100_clk_unregister, +}; + +static const struct hisi_gate_clock hi3798mv100_sysctrl_gate_clks[] = { + { HISTB_IR_CLK, "clk_ir", "24m", + CLK_SET_RATE_PARENT, 0x48, 4, 0, }, + { HISTB_TIMER01_CLK, "clk_timer01", "24m", + CLK_SET_RATE_PARENT, 0x48, 6, 0, }, + { HISTB_UART0_CLK, "clk_uart0", "83p3m", + CLK_SET_RATE_PARENT, 0x48, 12, 0, }, +}; + +static const struct hi3798_clks hi3798mv100_sysctrl_clks = { + .gate_clks = hi3798mv100_sysctrl_gate_clks, + .gate_clks_nums = ARRAY_SIZE(hi3798mv100_sysctrl_gate_clks), +}; + +static struct hisi_clock_data *hi3798mv100_sysctrl_clk_register( + struct platform_device *pdev) +{ + return hi3798_sysctrl_clk_register(pdev, &hi3798mv100_sysctrl_clks); +} + +static void hi3798mv100_sysctrl_clk_unregister(struct platform_device *pdev) +{ + hi3798_sysctrl_clk_unregister(pdev, &hi3798mv100_sysctrl_clks); +} + +static const struct hisi_crg_funcs hi3798mv100_sysctrl_funcs = { + .register_clks = hi3798mv100_sysctrl_clk_register, + .unregister_clks = hi3798mv100_sysctrl_clk_unregister, +}; + static const struct of_device_id hi3798_crg_match_table[] = { { .compatible = "hisilicon,hi3798cv200-crg", .data = &hi3798cv200_crg_funcs }, { .compatible = "hisilicon,hi3798cv200-sysctrl", .data = &hi3798cv200_sysctrl_funcs }, + { .compatible = "hisilicon,hi3798mv100-crg", + .data = &hi3798mv100_crg_funcs }, + { .compatible = "hisilicon,hi3798mv100-sysctrl", + .data = &hi3798mv100_sysctrl_funcs }, { } }; MODULE_DEVICE_TABLE(of, hi3798_crg_match_table);