Message ID | 20230321190118.3327360-3-bhupesh.sharma@linaro.org |
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State | New |
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Series |
arm64: dts: qcom: Enable Crypto Engine for a few Qualcomm SoCs
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Commit Message
Bhupesh Sharma
March 21, 2023, 7:01 p.m. UTC
Add crypto engine (CE) and CE BAM related nodes and definitions to
'sm6115.dtsi'.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
arch/arm64/boot/dts/qcom/sm6115.dtsi | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
Comments
On Wed, Mar 22, 2023 at 12:31:15AM +0530, Bhupesh Sharma wrote: > Add crypto engine (CE) and CE BAM related nodes and definitions to > 'sm6115.dtsi'. > > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm6115.dtsi | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi > index c56738633431..b2d2cdde41fa 100644 > --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi > @@ -664,6 +664,32 @@ usb_1_hsphy: phy@1613000 { > status = "disabled"; > }; > > + cryptobam: dma-controller@1b04000 { > + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; > + reg = <0x0 0x01b04000 0x0 0x24000>; > + interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; > + #dma-cells = <1>; > + qcom,ee = <0>; > + qcom,controlled-remotely; > + num-channels = <8>; > + qcom,num-ees = <2>; > + iommus = <&apps_smmu 0x84 0x11>, > + <&apps_smmu 0x86 0x11>, > + <&apps_smmu 0x94 0x11>, > + <&apps_smmu 0x96 0x11>; > + }; > + > + crypto: crypto@1b3a000 { > + compatible = "qcom,sm6115-qce", "qcom,sm8150-qce", "qcom,qce"; > + reg = <0x0 0x01b3a000 0x0 0x6000>; > + dmas = <&cryptobam 6>, <&cryptobam 7>; > + dma-names = "rx", "tx"; > + iommus = <&apps_smmu 0x84 0x11>, > + <&apps_smmu 0x86 0x11>, > + <&apps_smmu 0x94 0x11>, > + <&apps_smmu 0x96 0x11>; If you apply the 0x11 mask to the stream ID then the last two items here are identical to the first two (0x94 & ~0x11 = 0x84). Why are they needed? They look redundant to me. Thanks, Stephan
On Wed, 22 Mar 2023 at 02:09, Stephan Gerhold <stephan@gerhold.net> wrote: > > On Wed, Mar 22, 2023 at 12:31:15AM +0530, Bhupesh Sharma wrote: > > Add crypto engine (CE) and CE BAM related nodes and definitions to > > 'sm6115.dtsi'. > > > > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> > > --- > > arch/arm64/boot/dts/qcom/sm6115.dtsi | 26 ++++++++++++++++++++++++++ > > 1 file changed, 26 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi > > index c56738633431..b2d2cdde41fa 100644 > > --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi > > @@ -664,6 +664,32 @@ usb_1_hsphy: phy@1613000 { > > status = "disabled"; > > }; > > > > + cryptobam: dma-controller@1b04000 { > > + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; > > + reg = <0x0 0x01b04000 0x0 0x24000>; > > + interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; > > + #dma-cells = <1>; > > + qcom,ee = <0>; > > + qcom,controlled-remotely; > > + num-channels = <8>; > > + qcom,num-ees = <2>; > > + iommus = <&apps_smmu 0x84 0x11>, > > + <&apps_smmu 0x86 0x11>, > > + <&apps_smmu 0x94 0x11>, > > + <&apps_smmu 0x96 0x11>; > > + }; > > + > > + crypto: crypto@1b3a000 { > > + compatible = "qcom,sm6115-qce", "qcom,sm8150-qce", "qcom,qce"; > > + reg = <0x0 0x01b3a000 0x0 0x6000>; > > + dmas = <&cryptobam 6>, <&cryptobam 7>; > > + dma-names = "rx", "tx"; > > + iommus = <&apps_smmu 0x84 0x11>, > > + <&apps_smmu 0x86 0x11>, > > + <&apps_smmu 0x94 0x11>, > > + <&apps_smmu 0x96 0x11>; > > If you apply the 0x11 mask to the stream ID then the last two items here > are identical to the first two (0x94 & ~0x11 = 0x84). Why are they > needed? They look redundant to me. Thanks, I will check them out and fix them in v2. Regards.
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index c56738633431..b2d2cdde41fa 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -664,6 +664,32 @@ usb_1_hsphy: phy@1613000 { status = "disabled"; }; + cryptobam: dma-controller@1b04000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0x0 0x01b04000 0x0 0x24000>; + interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + num-channels = <8>; + qcom,num-ees = <2>; + iommus = <&apps_smmu 0x84 0x11>, + <&apps_smmu 0x86 0x11>, + <&apps_smmu 0x94 0x11>, + <&apps_smmu 0x96 0x11>; + }; + + crypto: crypto@1b3a000 { + compatible = "qcom,sm6115-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0x0 0x01b3a000 0x0 0x6000>; + dmas = <&cryptobam 6>, <&cryptobam 7>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x84 0x11>, + <&apps_smmu 0x86 0x11>, + <&apps_smmu 0x94 0x11>, + <&apps_smmu 0x96 0x11>; + }; + qfprom@1b40000 { compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; reg = <0x0 0x01b40000 0x0 0x7000>;