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From: Bhupesh Sharma <bhupesh.sharma@linaro.org>
To: linux-arm-msm@vger.kernel.org
Cc: agross@kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, andersson@kernel.org,
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Subject: [PATCH 1/5] arm64: dts: qcom: sdm845: Fix the BAM DMA engine
compatible string
Date: Wed, 22 Mar 2023 00:31:14 +0530
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| Series |
arm64: dts: qcom: Enable Crypto Engine for a few Qualcomm SoCs
|
|
Commit Message
Bhupesh Sharma
March 21, 2023, 7:01 p.m. UTC
As per documentation, Qualcomm SDM845 SoC supports BAM DMA
engine v1.7.4, so use the correct compatible strings.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Comments
On 21.03.2023 20:01, Bhupesh Sharma wrote: > As per documentation, Qualcomm SDM845 SoC supports BAM DMA > engine v1.7.4, so use the correct compatible strings. > > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > index 0fdd59a9feed..e8e9aa4da914 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > @@ -2628,7 +2628,7 @@ ufs_mem_phy_lanes: phy@1d87400 { > }; > > cryptobam: dma-controller@1dc4000 { > - compatible = "qcom,bam-v1.7.0"; > + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; > reg = <0 0x01dc4000 0 0x24000>; > interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; > clocks = <&rpmhcc RPMH_CE_CLK>;
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 0fdd59a9feed..e8e9aa4da914 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2628,7 +2628,7 @@ ufs_mem_phy_lanes: phy@1d87400 { }; cryptobam: dma-controller@1dc4000 { - compatible = "qcom,bam-v1.7.0"; + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0 0x01dc4000 0 0x24000>; interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rpmhcc RPMH_CE_CLK>;