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Tue, 21 Mar 2023 00:05:56 -0500 Received: from vijendar-X570-GAMING-X.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Tue, 21 Mar 2023 00:05:52 -0500 From: Vijendar Mukunda To: CC: , , , , , , , , , , "Vijendar Mukunda" , Bard Liao , Sanyog Kale , open list Subject: [PATCH V8 7/8] soundwire: amd: handle SoundWire wake enable interrupt Date: Tue, 21 Mar 2023 10:39:00 +0530 Message-ID: <20230321050901.115439-8-Vijendar.Mukunda@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230321050901.115439-1-Vijendar.Mukunda@amd.com> References: <20230321050901.115439-1-Vijendar.Mukunda@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT023:EE_|SA1PR12MB6797:EE_ X-MS-Office365-Filtering-Correlation-Id: dc6c1de3-c6a4-45ff-8a09-08db29c9f45c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: IdFOygQ2tBx4mqsnbICqO4bm5tc2MbvkbPwpUTh0DUccio4RbvHdZ1fi+UlxJe+r+nOGgukeGK/Cr6kbs0yNG8OvUQ5gdApZAXiaYDgUlsj0CAKb4Tv+oqCQxvnYgygl2hyMkH+RnQmvJ35xRswiI7tvWhA1bsvTFYNJdjfkbCFwBDWg9C8IilESR+XWgG7msE14UJSQBWYotetDwrbKzn3deCvPhIVi3UpiKmmA6WEKRhbEcgZe0iCjF220uGU+eSaCudA13bMziRkb5YWPaHwAVnC2dZaZaIY/ygxCJJOUeT9Ze5sidcF0uZ0oiBOX2RxdSQ8jTHmEgVLHTbcXQcumIX8Bz6VizbECeZNwdgXcUNjX+mN7V7cgql3VG6nw6UMD4OEUSVFC70bTO3XLWmIDzBK0iiT5BuTFbOLJ7EBSykCHh7+HSweJ2HYLjKum9ncUTJDL5tONo4OiZv2ZkkmofWMd8P+BZwns3vr20FYrJ76rLP2lvKK9AG0Xcy1DgkQqoPCI2WWezGWoyVCh5q1QvIB7CSpaNZemhAzFXvfCoiHlMhniPeDdLFnnwkiYXrSr0OXUMj+XXZebUosLKNfHezAoHTXmr2v2kG2if94xZuvezJJdsp56q+cOASBsD5JdtUvxm+vra7mag95dm1D/iQjz8kBX+W/B5jLFOWwmwqmg/0iYWjUobxf0C4x7V8uEP9s8CsVCl6NtFkcRbS9sOE1xXF8r9bcBskM7WNY= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(376002)(136003)(39860400002)(396003)(346002)(451199018)(40470700004)(46966006)(36840700001)(316002)(2616005)(82310400005)(70206006)(70586007)(8676002)(6666004)(6916009)(4326008)(40460700003)(86362001)(83380400001)(40480700001)(36756003)(47076005)(426003)(336012)(186003)(82740400003)(81166007)(7696005)(41300700001)(26005)(356005)(1076003)(36860700001)(54906003)(5660300002)(8936002)(966005)(2906002)(478600001)(36900700001);DIR:OUT;SFP:1101; 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Signed-off-by: Vijendar Mukunda Signed-off-by: Mastan Katragadda Reviewed-by: Pierre-Louis Bossart Link: https://lore.kernel.org/lkml/20230227154801.50319-8-Vijendar.Mukunda@amd.com --- drivers/soundwire/amd_manager.c | 10 ++++++++++ drivers/soundwire/amd_manager.h | 1 + 2 files changed, 11 insertions(+) diff --git a/drivers/soundwire/amd_manager.c b/drivers/soundwire/amd_manager.c index 6172b3cb84d4..d55706e87d83 100644 --- a/drivers/soundwire/amd_manager.c +++ b/drivers/soundwire/amd_manager.c @@ -831,6 +831,13 @@ static void amd_sdw_update_slave_status(u32 status_change_0to7, u32 status_chang } } +static void amd_sdw_process_wake_event(struct amd_sdw_manager *amd_manager) +{ + pm_request_resume(amd_manager->dev); + writel(0x00, amd_manager->acp_mmio + ACP_SW_WAKE_EN(amd_manager->instance)); + writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_8TO11); +} + static void amd_sdw_irq_thread(struct work_struct *work) { struct amd_sdw_manager *amd_manager = @@ -842,6 +849,9 @@ static void amd_sdw_irq_thread(struct work_struct *work) status_change_0to7 = readl(amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_0TO7); dev_dbg(amd_manager->dev, "[SDW%d] SDW INT: 0to7=0x%x, 8to11=0x%x\n", amd_manager->instance, status_change_0to7, status_change_8to11); + if (status_change_8to11 & AMD_SDW_WAKE_STAT_MASK) + return amd_sdw_process_wake_event(amd_manager); + if (status_change_8to11 & AMD_SDW_PREQ_INTR_STAT) { amd_sdw_read_and_process_ping_status(amd_manager); } else { diff --git a/drivers/soundwire/amd_manager.h b/drivers/soundwire/amd_manager.h index b101f4536230..5f040151a259 100644 --- a/drivers/soundwire/amd_manager.h +++ b/drivers/soundwire/amd_manager.h @@ -189,6 +189,7 @@ #define AMD_SDW_CLK_STOP_DONE 1 #define AMD_SDW_CLK_RESUME_REQ 2 #define AMD_SDW_CLK_RESUME_DONE 3 +#define AMD_SDW_WAKE_STAT_MASK BIT(16) static u32 amd_sdw_freq_tbl[AMD_SDW_MAX_FREQ_NUM] = { AMD_SDW_DEFAULT_CLK_FREQ,