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Mon, 20 Mar 2023 11:27:06 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Mon, 20 Mar 2023 11:27:05 -0700 Received: from sumitg-l4t.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.5 via Frontend Transport; Mon, 20 Mar 2023 11:27:00 -0700 From: Sumit Gupta To: , , , , , , , CC: , , , , , , , , , , , , , Subject: [Patch v3 10/11] memory: tegra: handle no BWMGR MRQ support in BPMP Date: Mon, 20 Mar 2023 23:54:40 +0530 Message-ID: <20230320182441.11904-11-sumitg@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230320182441.11904-1-sumitg@nvidia.com> References: <20230320182441.11904-1-sumitg@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT092:EE_|PH7PR12MB6979:EE_ X-MS-Office365-Filtering-Correlation-Id: e37ed870-55d1-4b49-0101-08db2970b734 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Mar 2023 18:27:08.8834 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e37ed870-55d1-4b49-0101-08db2970b734 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT092.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6979 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, SPF_HELO_PASS,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760914329443257567?= X-GMAIL-MSGID: =?utf-8?q?1760914329443257567?= If BPMP-FW doesn't support 'MRQ_BWMGR_INT', then the MC Client driver probe fails with 'EPROBE_DEFER' which it receives on calling the func 'devm_of_icc_get()'. Fix this by initializing the ICC even if the MRQ is missing and return 'EINVAL' from 'icc_set_bw()' instead of passing the request to BPMP-FW later when the BW request is made by client. Fixes: ("memory: tegra: add interconnect support for DRAM scaling in Tegra234") Signed-off-by: Sumit Gupta --- drivers/memory/tegra/tegra186-emc.c | 13 +++++++------ drivers/memory/tegra/tegra234.c | 6 ++++++ include/soc/tegra/mc.h | 2 +- 3 files changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/memory/tegra/tegra186-emc.c b/drivers/memory/tegra/tegra186-emc.c index 978be8f54de4..0d68a20fd376 100644 --- a/drivers/memory/tegra/tegra186-emc.c +++ b/drivers/memory/tegra/tegra186-emc.c @@ -343,13 +343,14 @@ static int tegra186_emc_probe(struct platform_device *pdev) mc = dev_get_drvdata(emc->dev->parent); if (mc && mc->soc->icc_ops) { - if (tegra_bpmp_mrq_is_supported(emc->bpmp, MRQ_BWMGR_INT)) { - err = tegra_emc_interconnect_init(emc); - if (err) - goto put_bpmp; - } else { + err = tegra_emc_interconnect_init(emc); + if (err) + goto put_bpmp; + + if (tegra_bpmp_mrq_is_supported(emc->bpmp, MRQ_BWMGR_INT)) + mc->bwmgr_mrq_supported = true; + else dev_info(&pdev->dev, "MRQ_BWMGR_INT not present\n"); - } } return 0; diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c index 0b608b820b28..5b4b359f7c71 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -828,6 +828,9 @@ static int tegra234_mc_icc_set(struct icc_node *src, struct icc_node *dst) if (src->id == dst->id) return 0; + if (!mc->bwmgr_mrq_supported) + return -EINVAL; + bpmp = of_tegra_bpmp_get(); if (IS_ERR(bpmp)) { ret = PTR_ERR(bpmp); @@ -874,6 +877,9 @@ static int tegra234_mc_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, struct icc_provider *p = node->provider; struct tegra_mc *mc = icc_provider_to_tegra_mc(p); + if (!mc->bwmgr_mrq_supported) + return -EINVAL; + if (node->id == TEGRA_ICC_MC_CPU_CLUSTER0 || node->id == TEGRA_ICC_MC_CPU_CLUSTER1 || node->id == TEGRA_ICC_MC_CPU_CLUSTER2) { diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 2fe6f0217a39..522b7679500c 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -234,7 +234,7 @@ struct tegra_mc { struct tegra_mc_timing *timings; unsigned int num_timings; unsigned int num_channels; - + bool bwmgr_mrq_supported; struct reset_controller_dev reset; struct icc_provider provider;