From patchwork Mon Mar 20 00:52:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 71924 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp944460wrt; Sun, 19 Mar 2023 17:54:26 -0700 (PDT) X-Google-Smtp-Source: AK7set+jIxO8EOFTG0G8J656dfexPTBE6VYI9PrvJn2qyYxbFS0P4PuRA6BU4ZX23Kw2SkWrZtSC X-Received: by 2002:a05:6a20:9384:b0:d9:ec4b:82b4 with SMTP id x4-20020a056a20938400b000d9ec4b82b4mr235314pzh.1.1679273666073; Sun, 19 Mar 2023 17:54:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1679273666; cv=none; d=google.com; s=arc-20160816; b=FC9FUntc/Y+04lHW3M3HyfGTwDizCznr7ZqlOqFk2TX+gQzE12sSeeUT6DIwQqYpLS 5vzms5fSiFJGz2uCujZQhTIF00WmNpX7iMWsH1hm6tSaZk2R92Hzu1X/xti5tVTE2ht4 uI5Kqk7bpoaZLI2O9BLPqShH+Sf4CPfhmGgej42SZoRlnhn1Q8SB9lnPUcd4hGW/BnVS KcgBuA3XaiAfghKhYYDdETs0hStux9BaLauBlvHqwRX9fFwpHLyoF61PibqIfveS+wmJ jScTTb15kiT54FmRyIu/vx1jYI6ihtH8T6DHLXcT+ENjDBeTTEVcG+MUAoLN+bdyZ6dy ilsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=f6j69U8rb6LM2iMJ3RaEJZhDDIX+GZ5IiMLSg3t4ZPc=; b=0fRO1piPUHL5Q9T3u3dVBA/QjOf0pmBQmP+ugkqvTo/9QkjQNzvdzjSGDQGEMiefuS Ey67r0rtKRV5SMa3IMDzr+bdsz1QqV7HgJdp7ZTYAwdajRlMxb6HgxVGishtJL83r+1t rzQKEReqB9bDXpi2LSlZOvzPbD8KjBJQ6GYWBJLhhF7WmnhvUf042fjqnDH6t9jTishv QWWCIz11C/wQLzukAdGpQwu1x18zleQoDEYGyDhQhIAgm6KjnI1epTaCSeue4HzZbKGP iYdkH85JJuiCJ7dAcHhnkQFMFJMH6/qWh519+ehVy0GWJvljU8VO2GvuWTr1A1XqU/Oi qDQA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id f5-20020a056a0022c500b005a8d684c05dsi9858876pfj.271.2023.03.19.17.54.13; Sun, 19 Mar 2023 17:54:26 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229764AbjCTAxZ (ORCPT + 99 others); Sun, 19 Mar 2023 20:53:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229662AbjCTAxL (ORCPT ); Sun, 19 Mar 2023 20:53:11 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 40B581A64B; Sun, 19 Mar 2023 17:53:09 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AD76C1063; Sun, 19 Mar 2023 17:53:52 -0700 (PDT) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9C3433F885; Sun, 19 Mar 2023 17:53:05 -0700 (PDT) From: Andre Przywara To: Rob Herring , Krzysztof Kozlowski , Chen-Yu Tsai , Samuel Holland , Jernej Skrabec Cc: linux-arm-kernel@lists.infradead.org, Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , =?utf-8?b?QW5kcsOhcyBTemVtesO2?= , Icenowy Zheng , Fabien Poussin , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Belisko Marek Subject: [PATCH v2 2/4] ARM: dts: sunxi: add Allwinner T113-s SoC .dtsi Date: Mon, 20 Mar 2023 00:52:47 +0000 Message-Id: <20230320005249.13403-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.7 In-Reply-To: <20230320005249.13403-1-andre.przywara@arm.com> References: <20230320005249.13403-1-andre.przywara@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760846063655559535?= X-GMAIL-MSGID: =?utf-8?q?1760846063655559535?= The Allwinner T113-s SoC is apparently using the same (or at least a very similar) die as the D1/D1s, but replaces the single RISC-V core with two Arm Cortex-A7 cores. Since the D1 core .dtsi already describes all common peripherals, we just need a DT describing the ARM specific peripherals: the CPU cores, the Generic Timer, the GIC and the PMU. We include the core .dtsi directly from the riscv DT directory. Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec --- arch/arm/boot/dts/sun8i-t113s.dtsi | 59 ++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-t113s.dtsi diff --git a/arch/arm/boot/dts/sun8i-t113s.dtsi b/arch/arm/boot/dts/sun8i-t113s.dtsi new file mode 100644 index 0000000000000..804aa197a24f8 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-t113s.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Arm Ltd. + +#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr + +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; + }; + }; + + gic: interrupt-controller@1c81000 { + compatible = "arm,gic-400"; + reg = <0x03021000 0x1000>, + <0x03022000 0x2000>, + <0x03024000 0x2000>, + <0x03026000 0x2000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; +};