From patchwork Fri Mar 17 07:51:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Achal Verma X-Patchwork-Id: 71120 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp203265wrt; Fri, 17 Mar 2023 00:53:50 -0700 (PDT) X-Google-Smtp-Source: AK7set98bGzZUaHEGb1d/l386YZaXPviIINTeBl62H+xRJc2OiN/s7iVDMggX3su15Zoh58/twrI X-Received: by 2002:a05:6a20:7fa3:b0:cd:345e:5b10 with SMTP id d35-20020a056a207fa300b000cd345e5b10mr11309355pzj.5.1679039630366; Fri, 17 Mar 2023 00:53:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1679039630; cv=none; d=google.com; s=arc-20160816; b=WKcRWdEAECjlaKYBnVgI5KXDeNECI3HbjWrJyk0E2EfFIRU3/8rnbfODZx+JIDhrz0 YdDK+mv8T/E08FpsX59NdFAxrfkfvmchu/a2KlQmrmn33getrxoWyIDEtSsSLN/aSQo9 hDD24sV9OkxWf7RfsErDbxis0jKKUNtAXBmAgrJQvnvDSKzGMcEIEH7NZjIhuEJDG8PF +vSFqmRiW/YvxnrA8xgCCG/whxICqYoixc/15W+Szm132sR2BR6UrrVAxxqm61Y8gCq0 HeCk8ILE3RaPzDk0CXnepxId9vwfQayvhtl0A6Kz6cJfBI7NCDBApHf3F1IYzKYFuvAx QiIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=TISRczCqqClgTnuh9Jgbp4YdFIC7Href1UTZ0gVUQ5I=; b=NJbINuc0cN2SENCPU8Xf5iNf47XoIo9u5HP6B72drtdhi/id4t8giUTl5o6uOqUOXV oSfbrMlAJQHRsOZCJjpzL+dKeHSL2tdsQ6hkQ/pph1Iag7OL8oRDMZDYgzRrjN4d0SQk Z1qTlJ590rpWfBG+MZV/7/AqpV4al4uMfeSb0XZqkL10m3gqlV0pSY6vVJvqgfu49HyU bHu7XXcWleHVFl9RqntX9uLOo3zy2jYs5mHC1StNDYq7LCas3uSVHnjGarm+PhoEgxxB GtAAGPUHZPEwRkryp32KpVF5LGecmCI0QdqujzjSlCQjd4Qgclk/sXOUpW/F1HrwWbEl WoqQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=jaMqWZ5q; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id j7-20020a056a00174700b006255fe95314si2002066pfc.60.2023.03.17.00.53.37; Fri, 17 Mar 2023 00:53:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=jaMqWZ5q; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230427AbjCQHv6 (ORCPT + 99 others); Fri, 17 Mar 2023 03:51:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58112 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230383AbjCQHvv (ORCPT ); Fri, 17 Mar 2023 03:51:51 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1881AC5AC9; Fri, 17 Mar 2023 00:51:42 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 32H7pQFE008664; Fri, 17 Mar 2023 02:51:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1679039486; bh=TISRczCqqClgTnuh9Jgbp4YdFIC7Href1UTZ0gVUQ5I=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jaMqWZ5qBPyQA9WMOOvu0DfCBAw1ihhRm9e/tljBb5g/8vuNYFWURmsPhVMfYzbSw R9UB2teEoReDNpyQMuipQBJm+i3yYtPQdG8u6bXW3bFHPHv7m4RPj3KEfDlnEX692Q ZCEais0bbVQtg39nWls9UKEqnMqEfOA8eL6Tnj8c= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 32H7pQD7119567 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 17 Mar 2023 02:51:26 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Fri, 17 Mar 2023 02:51:26 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Fri, 17 Mar 2023 02:51:26 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32H7pP24113752; Fri, 17 Mar 2023 02:51:26 -0500 From: Achal Verma To: Lorenzo Pieralisi , Krzysztof Wilczy_ski , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Vignesh Raghavendra , Dhananjay Vilasrao Kangude , Anindita Das , Yuan Zhao , Milind Parab CC: , , , , , Achal Verma Subject: [PATCH v11 3/5] PCI: j721e: Add PCIe 4x lane selection support Date: Fri, 17 Mar 2023 13:21:18 +0530 Message-ID: <20230317075120.506267-4-a-verma1@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230317075120.506267-1-a-verma1@ti.com> References: <20230317075120.506267-1-a-verma1@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760600659799419014?= X-GMAIL-MSGID: =?utf-8?q?1760600659799419014?= From: Matt Ranostay Add support for setting of two-bit field that allows selection of 4x lane PCIe which was previously limited to only 2x lanes. Signed-off-by: Matt Ranostay Reviewed-by: Vignesh Raghavendra Reviewed-by: Roger Quadros Signed-off-by: Achal Verma --- drivers/pci/controller/cadence/pci-j721e.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index f4dc2c5abedb..58dcac9021e4 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -42,7 +42,6 @@ enum link_status { }; #define J721E_MODE_RC BIT(7) -#define LANE_COUNT_MASK BIT(8) #define LANE_COUNT(n) ((n) << 8) #define GENERATION_SEL_MASK GENMASK(1, 0) @@ -52,6 +51,7 @@ struct j721e_pcie { struct clk *refclk; u32 mode; u32 num_lanes; + u32 max_lanes; void __iomem *user_cfg_base; void __iomem *intd_cfg_base; u32 linkdown_irq_regfield; @@ -205,11 +205,15 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie, { struct device *dev = pcie->cdns_pcie->dev; u32 lanes = pcie->num_lanes; + u32 mask = BIT(8); u32 val = 0; int ret; + if (pcie->max_lanes == 4) + mask = GENMASK(9, 8); + val = LANE_COUNT(lanes - 1); - ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val); + ret = regmap_update_bits(syscon, offset, mask, val); if (ret) dev_err(dev, "failed to set link count\n"); @@ -441,7 +445,9 @@ static int j721e_pcie_probe(struct platform_device *pdev) dev_warn(dev, "num-lanes property not provided or invalid, setting num-lanes to 1\n"); num_lanes = 1; } + pcie->num_lanes = num_lanes; + pcie->max_lanes = data->max_lanes; if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48))) return -EINVAL;