[v3] arm64: dts: mediatek: Add cpufreq nodes for MT8192
Commit Message
Add the cpufreq nodes for MT8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
Change from v2:
Fix wrong performance-domains
[Allen-KH Cheng <allen-kh.cheng@mediatek.com>]
---
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
Comments
Il 17/03/23 07:19, Allen-KH Cheng ha scritto:
> Add the cpufreq nodes for MT8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
On Asurada-Spherion Chromebook:
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
On Fri, Mar 17, 2023 at 02:19:44PM +0800, Allen-KH Cheng wrote:
> Add the cpufreq nodes for MT8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Tested on Asurada Spherion Chromebook as well. In particular, verified that
applying this commit makes suspend/resume work. Before, it would hang during
resume:
Enabling non-boot CPUs ...
Detected VIPT I-cache on CPU1
GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
But with this commit applied the machine is able to proceed bringing up the
secondary processors and complete resume.
Thanks,
Nícolas
On Sat, Mar 18, 2023 at 3:55 AM Nícolas F. R. A. Prado
<nfraprado@collabora.com> wrote:
>
> On Fri, Mar 17, 2023 at 02:19:44PM +0800, Allen-KH Cheng wrote:
> > Add the cpufreq nodes for MT8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
>
> Tested on Asurada Spherion Chromebook as well. In particular, verified that
> applying this commit makes suspend/resume work. Before, it would hang during
> resume:
>
> Enabling non-boot CPUs ...
> Detected VIPT I-cache on CPU1
> GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
> CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
>
> But with this commit applied the machine is able to proceed bringing up the
> secondary processors and complete resume.
Ping on this patch.
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
On 30/05/2023 09:29, Chen-Yu Tsai wrote:
> On Sat, Mar 18, 2023 at 3:55 AM Nícolas F. R. A. Prado
> <nfraprado@collabora.com> wrote:
>>
>> On Fri, Mar 17, 2023 at 02:19:44PM +0800, Allen-KH Cheng wrote:
>>> Add the cpufreq nodes for MT8192 SoC.
>>>
>>> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
>>
>> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
>> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
>>
>> Tested on Asurada Spherion Chromebook as well. In particular, verified that
>> applying this commit makes suspend/resume work. Before, it would hang during
>> resume:
>>
>> Enabling non-boot CPUs ...
>> Detected VIPT I-cache on CPU1
>> GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
>> CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
>>
>> But with this commit applied the machine is able to proceed bringing up the
>> secondary processors and complete resume.
>
> Ping on this patch.
>
> Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Applied now, thanks for the ping.
Regards,
Matthias
@@ -70,6 +70,7 @@
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
capacity-dmips-mhz = <530>;
};
@@ -87,6 +88,7 @@
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
capacity-dmips-mhz = <530>;
};
@@ -104,6 +106,7 @@
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
capacity-dmips-mhz = <530>;
};
@@ -121,6 +124,7 @@
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
capacity-dmips-mhz = <530>;
};
@@ -138,6 +142,7 @@
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
+ performance-domains = <&performance 1>;
capacity-dmips-mhz = <1024>;
};
@@ -155,6 +160,7 @@
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
+ performance-domains = <&performance 1>;
capacity-dmips-mhz = <1024>;
};
@@ -172,6 +178,7 @@
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
+ performance-domains = <&performance 1>;
capacity-dmips-mhz = <1024>;
};
@@ -189,6 +196,7 @@
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
+ performance-domains = <&performance 1>;
capacity-dmips-mhz = <1024>;
};
@@ -318,6 +326,12 @@
compatible = "simple-bus";
ranges;
+ performance: performance-controller@11bc10 {
+ compatible = "mediatek,cpufreq-hw";
+ reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
+ #performance-domain-cells = <1>;
+ };
+
gic: interrupt-controller@c000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <4>;