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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id kz11-20020a170902f9cb00b001a0667822c8sm2740003plb.94.2023.03.15.00.29.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 00:29:28 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, schung@nuvoton.com, Jacky Huang Subject: [PATCH 08/15] dt-bindings: clock: Document ma35d1 clock controller bindings Date: Wed, 15 Mar 2023 07:28:55 +0000 Message-Id: <20230315072902.9298-9-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230315072902.9298-1-ychuang570808@gmail.com> References: <20230315072902.9298-1-ychuang570808@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760418825742147667?= X-GMAIL-MSGID: =?utf-8?q?1760418825742147667?= From: Jacky Huang Add documentation to describe nuvoton ma35d1 clock driver bindings. Signed-off-by: Jacky Huang --- .../bindings/clock/nuvoton,ma35d1-clk.yaml | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml diff --git a/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml new file mode 100644 index 000000000000..5c2dea071b38 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nuvoton,ma35d1-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 Clock Controller Module Binding + +maintainers: + - Chi-Fang Li + - Jacky Huang + +description: | + The MA35D1 clock controller generates clocks for the whole chip, + including system clocks and all peripheral clocks. + + See also: + include/dt-bindings/clock/ma35d1-clk.h + +properties: + compatible: + items: + - const: nuvoton,ma35d1-clk + - const: syscon + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: clk_hxt + + assigned-clocks: + maxItems: 5 + + assigned-clock-rates: + maxItems: 5 + + nuvoton,pll-mode: + description: + A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL, + EPLL, and VPLL in sequential. The operation mode value 0 is for + integer mode, 1 is for fractional mode, and 2 is for spread + spectrum mode. + $ref: /schemas/types.yaml#/definitions/uint32-array + maxItems: 5 + items: + minimum: 0 + maximum: 2 + + nuvoton,sys: + description: + Phandle to the system management controller. + $ref: "/schemas/types.yaml#/definitions/phandle-array" + +required: + - compatible + - reg + - "#clock-cells" + - clocks + - clock-names + - nuvoton,sys + +additionalProperties: false + +examples: + - | + #include + + clk: clock-controller@40460200 { + compatible = "nuvoton,ma35d1-clk", "syscon"; + reg = <0x40460200 0x100>; + #clock-cells = <1>; + clocks = <&clk_hxt>; + clock-names = "clk_hxt"; + nuvoton,sys = <&sys>; + }; +...