diff mbox series

[v4,05/18] PCI: qcom: Use lower case for hex

Message ID	20230315064255.15591-6-manivannan.sadhasivam@linaro.org
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Subject: [PATCH v4 05/18] PCI: qcom: Use lower case for hex Date: Wed, 15 Mar 2023 12:12:42 +0530 Message-Id: <20230315064255.15591-6-manivannan.sadhasivam@linaro.org> In-Reply-To: <20230315064255.15591-1-manivannan.sadhasivam@linaro.org> References: <20230315064255.15591-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	Qcom PCIe cleanups and improvements \| [v4,00/18] Qcom PCIe cleanups and improvements [v4,01/18] PCI: qcom: Remove PCIE20_ prefix from register definitions [v4,02/18] PCI: qcom: Sort and group registers and bitfield definitions [v4,03/18] PCI: qcom: Use bitfield definitions for register fields [v4,04/18] PCI: qcom: Add missing macros for register fields [v4,05/18] PCI: qcom: Use lower case for hex [v4,06/18] PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.1.0 [v4,07/18] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 1.0.0 [v4,08/18] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.2 [v4,09/18] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.3 [v4,10/18] PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.3.3 [v4,11/18] PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.4.0 [v4,12/18] PCI: qcom: Use macros for defining total no. of clocks & supplies [v4,13/18] PCI: qcom: Rename qcom_pcie_config_sid_sm8250() to reflect IP version [v4,14/18] dt-bindings: PCI: qcom: Add "mhi" register region to supported SoCs [v4,15/18] arm64: dts: qcom: sdm845: Add "mhi" region to the PCIe nodes [v4,16/18] arm64: dts: qcom: sm8250: Add "mhi" region to the PCIe nodes [v4,17/18] arm64: dts: qcom: sc8280xp: Add "mhi" region to the PCIe nodes [v4,18/18] PCI: qcom: Expose link transition counts via debugfs

Commit Message

Manivannan Sadhasivam March 15, 2023, 6:42 a.m. UTC

  To maintain uniformity, let's use lower case for representing hexadecimal
numbers.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

Comments

Konrad Dybcio March 15, 2023, 10:34 a.m. UTC | #1

On 15.03.2023 07:42, Manivannan Sadhasivam wrote:
> To maintain uniformity, let's use lower case for representing hexadecimal
> numbers.
> 
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
To be fair, preprocessor defines are the only place where uppercase
hex is widely used

Konrad
>  drivers/pci/controller/dwc/pcie-qcom.c | 14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 926a531fda3a..4179ac973147 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -39,17 +39,17 @@
>  #define PARF_PCS_DEEMPH				0x34
>  #define PARF_PCS_SWING				0x38
>  #define PARF_PHY_CTRL				0x40
> -#define PARF_PHY_REFCLK				0x4C
> +#define PARF_PHY_REFCLK				0x4c
>  #define PARF_CONFIG_BITS			0x50
>  #define PARF_DBI_BASE_ADDR			0x168
> -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x16C /* Register offset specific to IP ver 2.3.3 */
> +#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x16c /* Register offset specific to IP ver 2.3.3 */
>  #define PARF_MHI_CLOCK_RESET_CTRL		0x174
>  #define PARF_AXI_MSTR_WR_ADDR_HALT		0x178
> -#define PARF_AXI_MSTR_WR_ADDR_HALT_V2		0x1A8
> -#define PARF_Q2A_FLUSH				0x1AC
> -#define PARF_LTSSM				0x1B0
> +#define PARF_AXI_MSTR_WR_ADDR_HALT_V2		0x1a8
> +#define PARF_Q2A_FLUSH				0x1ac
> +#define PARF_LTSSM				0x1b0
>  #define PARF_SID_OFFSET				0x234
> -#define PARF_BDF_TRANSLATE_CFG			0x24C
> +#define PARF_BDF_TRANSLATE_CFG			0x24c
>  #define PARF_SLV_ADDR_SPACE_SIZE		0x358
>  #define PARF_DEVICE_TYPE			0x1000
>  #define PARF_BDF_TO_SID_TABLE_N			0x2000
> @@ -60,7 +60,7 @@
>  /* DBI registers */
>  #define AXI_MSTR_RESP_COMP_CTRL0		0x818
>  #define AXI_MSTR_RESP_COMP_CTRL1		0x81c
> -#define MISC_CONTROL_1_REG			0x8BC
> +#define MISC_CONTROL_1_REG			0x8bc
>  
>  /* PARF_SYS_CTRL register fields */
>  #define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN	BIT(29)

Manivannan Sadhasivam March 15, 2023, 1:31 p.m. UTC | #2

On Wed, Mar 15, 2023 at 11:34:13AM +0100, Konrad Dybcio wrote:
> 
> 
> On 15.03.2023 07:42, Manivannan Sadhasivam wrote:
> > To maintain uniformity, let's use lower case for representing hexadecimal
> > numbers.
> > 
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > ---
> To be fair, preprocessor defines are the only place where uppercase
> hex is widely used
> 

I perfer lower hex all over the driver and in this case, I also want to match
what is being done for pcie-qcom-ep so that it helps me in maintaining both
drivers.

Thanks,
Mani

> Konrad
> >  drivers/pci/controller/dwc/pcie-qcom.c | 14 +++++++-------
> >  1 file changed, 7 insertions(+), 7 deletions(-)
> > 
> > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> > index 926a531fda3a..4179ac973147 100644
> > --- a/drivers/pci/controller/dwc/pcie-qcom.c
> > +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> > @@ -39,17 +39,17 @@
> >  #define PARF_PCS_DEEMPH				0x34
> >  #define PARF_PCS_SWING				0x38
> >  #define PARF_PHY_CTRL				0x40
> > -#define PARF_PHY_REFCLK				0x4C
> > +#define PARF_PHY_REFCLK				0x4c
> >  #define PARF_CONFIG_BITS			0x50
> >  #define PARF_DBI_BASE_ADDR			0x168
> > -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x16C /* Register offset specific to IP ver 2.3.3 */
> > +#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x16c /* Register offset specific to IP ver 2.3.3 */
> >  #define PARF_MHI_CLOCK_RESET_CTRL		0x174
> >  #define PARF_AXI_MSTR_WR_ADDR_HALT		0x178
> > -#define PARF_AXI_MSTR_WR_ADDR_HALT_V2		0x1A8
> > -#define PARF_Q2A_FLUSH				0x1AC
> > -#define PARF_LTSSM				0x1B0
> > +#define PARF_AXI_MSTR_WR_ADDR_HALT_V2		0x1a8
> > +#define PARF_Q2A_FLUSH				0x1ac
> > +#define PARF_LTSSM				0x1b0
> >  #define PARF_SID_OFFSET				0x234
> > -#define PARF_BDF_TRANSLATE_CFG			0x24C
> > +#define PARF_BDF_TRANSLATE_CFG			0x24c
> >  #define PARF_SLV_ADDR_SPACE_SIZE		0x358
> >  #define PARF_DEVICE_TYPE			0x1000
> >  #define PARF_BDF_TO_SID_TABLE_N			0x2000
> > @@ -60,7 +60,7 @@
> >  /* DBI registers */
> >  #define AXI_MSTR_RESP_COMP_CTRL0		0x818
> >  #define AXI_MSTR_RESP_COMP_CTRL1		0x81c
> > -#define MISC_CONTROL_1_REG			0x8BC
> > +#define MISC_CONTROL_1_REG			0x8bc
> >  
> >  /* PARF_SYS_CTRL register fields */
> >  #define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN	BIT(29)

diff mbox series

Patch

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 926a531fda3a..4179ac973147 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -39,17 +39,17 @@ 
 #define PARF_PCS_DEEMPH				0x34
 #define PARF_PCS_SWING				0x38
 #define PARF_PHY_CTRL				0x40
-#define PARF_PHY_REFCLK				0x4C
+#define PARF_PHY_REFCLK				0x4c
 #define PARF_CONFIG_BITS			0x50
 #define PARF_DBI_BASE_ADDR			0x168
-#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x16C /* Register offset specific to IP ver 2.3.3 */
+#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x16c /* Register offset specific to IP ver 2.3.3 */
 #define PARF_MHI_CLOCK_RESET_CTRL		0x174
 #define PARF_AXI_MSTR_WR_ADDR_HALT		0x178
-#define PARF_AXI_MSTR_WR_ADDR_HALT_V2		0x1A8
-#define PARF_Q2A_FLUSH				0x1AC
-#define PARF_LTSSM				0x1B0
+#define PARF_AXI_MSTR_WR_ADDR_HALT_V2		0x1a8
+#define PARF_Q2A_FLUSH				0x1ac
+#define PARF_LTSSM				0x1b0
 #define PARF_SID_OFFSET				0x234
-#define PARF_BDF_TRANSLATE_CFG			0x24C
+#define PARF_BDF_TRANSLATE_CFG			0x24c
 #define PARF_SLV_ADDR_SPACE_SIZE		0x358
 #define PARF_DEVICE_TYPE			0x1000
 #define PARF_BDF_TO_SID_TABLE_N			0x2000
@@ -60,7 +60,7 @@ 
 /* DBI registers */
 #define AXI_MSTR_RESP_COMP_CTRL0		0x818
 #define AXI_MSTR_RESP_COMP_CTRL1		0x81c
-#define MISC_CONTROL_1_REG			0x8BC
+#define MISC_CONTROL_1_REG			0x8bc
 
 /* PARF_SYS_CTRL register fields */
 #define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN	BIT(29)