Message ID | 20230314121754.297264-1-nava.kishore.manne@amd.com |
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State | New |
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Tue, 14 Mar 2023 07:17:56 -0500 From: Nava kishore Manne <nava.kishore.manne@amd.com> To: <mdf@kernel.org>, <hao.wu@intel.com>, <yilun.xu@intel.com>, <trix@redhat.com>, <michal.simek@xilinx.com>, <linux-fpga@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH] fpga: zynq: Add parse_header ops support Date: Tue, 14 Mar 2023 17:47:54 +0530 Message-ID: <20230314121754.297264-1-nava.kishore.manne@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT097:EE_|PH7PR12MB8153:EE_ X-MS-Office365-Filtering-Correlation-Id: 587d42ae-afa6-4497-512c-08db2486265f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: YWsIGHcTjlHWJ1q8w+mmBCj7mxFNlDe7ED7ExOpSam+iAspTu8LUMhbQWL43EjTuMAAtAclEZvIm63/098mgqM/qM6JsGnlOFYNNE+eTOdkcMKTNCcG/oUF/LAHx4aY3aEIawnX9CmpTruZTqz7DGqEPVsGh9dr6J/CLYTHoQVYfnthzU6htdlpI+1/R7RONBNsE1iuphhW6WPq2YfIpqAQagIUA2DpW5aWbxH+yg4Ed6HZZmaNjv+6yRrIxElWumy36HhgSlhHFcu7c+swwiWFNNY3qCcdNnRCJm/zkZYG7wsSE+E9GQGdl/V+ZHJ3m0yPkXwplM9VwGt61EBfCLrpKT+vYwSg1rFDkOccbcVnhKtXN86wFbxoYZTdFMUW3aBxPpjEZM9LJfgxuskMUs/vgYMuaQfOS1EoTMZQA3aEXMz4ZZM9KunsH+hQvFIJLun5SLHo6ateoERfx0y7rUr5KWCrNHRSUpHA8w8aRZjega431VaW8Sfw6aq6oP40vYegTzy0Rxx37rp8bvdRbJi7fmKFBUawSOjwTRJXXzMbxffPpFshtinMihW83rwXfq1cgYP1KraC8j+s3ZZbkEepHkRBo7Vw2N27P4iD+9+nVHl3cDo2lRxQ4lAfjhWQeI1X4iiBZCiq+RWk2qfQNzOYwZJE9IseqQvKYGngwziiWsQE/Mz/R2eA8ETcVHYFD5+mUyUj54vHYxHisccX5zqi5YGjC/8Bflcf8E1dyHZgCmlTmt3ZNg5PyVEZNuviy X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(39860400002)(136003)(346002)(396003)(376002)(451199018)(36840700001)(40470700004)(46966006)(336012)(47076005)(426003)(316002)(110136005)(40460700003)(103116003)(36756003)(40480700001)(356005)(16526019)(86362001)(82740400003)(36860700001)(83380400001)(82310400005)(186003)(81166007)(1076003)(26005)(2616005)(5660300002)(478600001)(41300700001)(8676002)(2906002)(8936002)(70586007)(70206006)(36900700001)(2101003);DIR:OUT;SFP:1101; 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fpga: zynq: Add parse_header ops support
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Commit Message
Manne, Nava kishore
March 14, 2023, 12:17 p.m. UTC
The commit 3cc624beba63 ("fpga: fpga-mgr: support bitstream offset in
image buffer") added a new parse_header ops to handle the header related
stuff in the fpga framework. So moved the header validation logic from
write_init() to parse_header().
Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com>
---
drivers/fpga/zynq-fpga.c | 23 ++++++++++++++++-------
1 file changed, 16 insertions(+), 7 deletions(-)
Comments
On 2023-03-14 at 17:47:54 +0530, Nava kishore Manne wrote: > The commit 3cc624beba63 ("fpga: fpga-mgr: support bitstream offset in > image buffer") added a new parse_header ops to handle the header related > stuff in the fpga framework. So moved the header validation logic from > write_init() to parse_header(). > > Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com> > --- > drivers/fpga/zynq-fpga.c | 23 ++++++++++++++++------- > 1 file changed, 16 insertions(+), 7 deletions(-) > > diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c > index ae0da361e6c6..6e5df0193028 100644 > --- a/drivers/fpga/zynq-fpga.c > +++ b/drivers/fpga/zynq-fpga.c > @@ -248,6 +248,21 @@ static bool zynq_fpga_has_sync(const u8 *buf, size_t count) > return false; > } > > +static int zynq_fpga_ops_parse_header(struct fpga_manager *mgr, > + struct fpga_image_info *info, > + const char *buf, size_t count) > +{ > + if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) { > + if (!zynq_fpga_has_sync(buf, count)) { FPGA manager may pass in the whole image if it is already mapped, maybe only info->header_size should be checked? Thanks, Yilun > + dev_err(&mgr->dev, > + "Invalid bitstream, could not find a sync word. Bitstream must be a byte swapped .bin file\n"); > + return -EINVAL; > + } > + } > + > + return 0; > +} > + > static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, > struct fpga_image_info *info, > const char *buf, size_t count) > @@ -275,13 +290,6 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, > > /* don't globally reset PL if we're doing partial reconfig */ > if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) { > - if (!zynq_fpga_has_sync(buf, count)) { > - dev_err(&mgr->dev, > - "Invalid bitstream, could not find a sync word. Bitstream must be a byte swapped .bin file\n"); > - err = -EINVAL; > - goto out_err; > - } > - > /* assert AXI interface resets */ > regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET, > FPGA_RST_ALL_MASK); > @@ -545,6 +553,7 @@ static enum fpga_mgr_states zynq_fpga_ops_state(struct fpga_manager *mgr) > static const struct fpga_manager_ops zynq_fpga_ops = { > .initial_header_size = 128, > .state = zynq_fpga_ops_state, > + .parse_header = zynq_fpga_ops_parse_header, > .write_init = zynq_fpga_ops_write_init, > .write_sg = zynq_fpga_ops_write, > .write_complete = zynq_fpga_ops_write_complete, > -- > 2.25.1 >
diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c index ae0da361e6c6..6e5df0193028 100644 --- a/drivers/fpga/zynq-fpga.c +++ b/drivers/fpga/zynq-fpga.c @@ -248,6 +248,21 @@ static bool zynq_fpga_has_sync(const u8 *buf, size_t count) return false; } +static int zynq_fpga_ops_parse_header(struct fpga_manager *mgr, + struct fpga_image_info *info, + const char *buf, size_t count) +{ + if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) { + if (!zynq_fpga_has_sync(buf, count)) { + dev_err(&mgr->dev, + "Invalid bitstream, could not find a sync word. Bitstream must be a byte swapped .bin file\n"); + return -EINVAL; + } + } + + return 0; +} + static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, struct fpga_image_info *info, const char *buf, size_t count) @@ -275,13 +290,6 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, /* don't globally reset PL if we're doing partial reconfig */ if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) { - if (!zynq_fpga_has_sync(buf, count)) { - dev_err(&mgr->dev, - "Invalid bitstream, could not find a sync word. Bitstream must be a byte swapped .bin file\n"); - err = -EINVAL; - goto out_err; - } - /* assert AXI interface resets */ regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET, FPGA_RST_ALL_MASK); @@ -545,6 +553,7 @@ static enum fpga_mgr_states zynq_fpga_ops_state(struct fpga_manager *mgr) static const struct fpga_manager_ops zynq_fpga_ops = { .initial_header_size = 128, .state = zynq_fpga_ops_state, + .parse_header = zynq_fpga_ops_parse_header, .write_init = zynq_fpga_ops_write_init, .write_sg = zynq_fpga_ops_write, .write_complete = zynq_fpga_ops_write_complete,