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From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: andersson@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, bp@alien8.de,
tony.luck@intel.com
Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org,
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Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Subject: [PATCH v7 01/13] dt-bindings: arm: msm: Update the maintainers for
LLCC
Date: Tue, 14 Mar 2023 11:07:13 +0530
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| Series |
Qcom: LLCC/EDAC: Fix base address used for LLCC banks
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Commit Message
Manivannan Sadhasivam
March 14, 2023, 5:37 a.m. UTC
Both Rishabh and Sai have left Qualcomm, and there is no evidence of them
maintaining with a new identity. So their entry needs to be removed.
Listed Bjorn as the interim maintainer until someone volunteers to maintain
this binding.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
Comments
On 14/03/2023 06:37, Manivannan Sadhasivam wrote: > Both Rishabh and Sai have left Qualcomm, and there is no evidence of them > maintaining with a new identity. So their entry needs to be removed. > > Listed Bjorn as the interim maintainer until someone volunteers to maintain > this binding. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 38efcad56dbd..6570b808fd0d 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -7,8 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Last Level Cache Controller maintainers: - - Rishabh Bhatnagar <rishabhb@codeaurora.org> - - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> + - Bjorn Andersson <andersson@kernel.org> description: | LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,