diff mbox series

[v2] arm64: dts: qcom: qdu1000: Add LLCC/system-cache-controller

Message ID 20230313125731.17745-1-quic_kbajaj@quicinc.com
State New
Headers
Series [v2] arm64: dts: qcom: qdu1000: Add LLCC/system-cache-controller |

Commit Message

Komal Bajaj March 13, 2023, 12:57 p.m. UTC 
  Add a DT node for Last level cache (aka. system cache) controller
which provides control over the last level cache present on QDU1000
and QRU1000 SoCs.

Changes in v2:
  - Addressing comments from Konrad.

Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qdu1000.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

Comments

Bjorn Andersson April 5, 2023, 4:09 a.m. UTC | #1 
On Mon, 13 Mar 2023 18:27:31 +0530, Komal Bajaj wrote:
> Add a DT node for Last level cache (aka. system cache) controller
> which provides control over the last level cache present on QDU1000
> and QRU1000 SoCs.
> 
> Changes in v2:
>   - Addressing comments from Konrad.
> 
> [...]

Applied, thanks!

[1/1] arm64: dts: qcom: qdu1000: Add LLCC/system-cache-controller
      commit: 6209038f131fee84ff1536dc59864f54d06740f2

Best regards,
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
index f234159d2060..911ade2faa19 100644
--- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
@@ -1320,6 +1320,18 @@  gem_noc: interconnect@19100000 {
 			qcom,bcm-voters = <&apps_bcm_voter>;
 			#interconnect-cells = <2>;
 		};
+
+		system-cache-controller@19200000 {
+			compatible = "qcom,qdu1000-llcc";
+			reg = <0 0x19200000 0 0xd80000>,
+			      <0 0x1a200000 0 0x80000>,
+			      <0 0x221c8128 0 0x4>;
+			reg-names = "llcc_base",
+				    "llcc_broadcast_base",
+				    "multi_channel_register";
+			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+			multi-ch-bit-off = <24 2>;
+		};
 	};
 
 	timer {