From patchwork Sun Mar 12 00:44:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 68227 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp516877wrd; Sat, 11 Mar 2023 16:56:47 -0800 (PST) X-Google-Smtp-Source: AK7set++Wv6SENOMmH+t7+csAh4fD3t5UQvc3QNs9SV3eGkLQxLy2T9Ritq4LfDKjipLzt9F04gj X-Received: by 2002:a62:30c6:0:b0:5a9:c942:7294 with SMTP id w189-20020a6230c6000000b005a9c9427294mr22093751pfw.34.1678582607504; Sat, 11 Mar 2023 16:56:47 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1678582607; cv=pass; d=google.com; s=arc-20160816; b=P7Xy8QSqVuAaw/FxdB+OQH7TC6O69ASQFfCtXE3bOSt9scRkrG8ipgqymAGlxljWxg nziw9mm2xmcAPg680rUdHYyNZAVZ5UKAWPEgu5lImI4wCaVddBQvjxPxswcBglMBJ2xo b05Ex3EIH+GB4FOZAan0X+1m/tMwAheXb0mQ3gAM+ME4wlTto1ZGIJCrhWBJhxy+yeKn LKQqnnTs/TCmeey6Hvq32GF9qIcNu1uXnp+v1oYbSqBOfcZItzht4x7uEJ7ep1YMweYr 0/eNr1j0J73Lxe1yWuzbLIU0hy+BFvQrFpnkJd9UAewSzxP5zvHI5qCRwN0QXlDSULKO QYhg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=w/oYrqJ2MVHAPXs4YEdRHbzeuMzFW5jeOoSN8M0D6iw=; b=MdT1el2fNjtxNry1uZLaIm4qvNB3CrvvIJuEDRKibIsLdOLv4pr/gSTMglQxdSf5vR WippDz4dSuDq5aVKWtdrKErFuX5MzELQYZgcwftZ0GicpAzA3hPVqZVLWsgJXaLXVGU6 F7r5YUba2zWoGsZjZvrEuQtG7CkwD4mdQvlmwgCwdFnOJXpCFL5AD9RwK4ONWCiJdvSW wOkgt7ZtT2H/84KCJ8fXhA+ZJWBlq6m7iowrkNhP9dlwJCrsWiAQhEFVowo92xw1zbov fCcET+Dq2EWQZt4M8cWZKxCVaYATkbL4BTnB4wOuVki8GHqv5ncE51XIVLyAv7la8JdJ 4BQQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=ligK2Xir; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id bm18-20020a656e92000000b004fd0907ae7fsi3066641pgb.600.2023.03.11.16.56.33; Sat, 11 Mar 2023 16:56:47 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=ligK2Xir; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229922AbjCLAs3 (ORCPT + 99 others); Sat, 11 Mar 2023 19:48:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43200 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229912AbjCLAsZ (ORCPT ); Sat, 11 Mar 2023 19:48:25 -0500 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on20615.outbound.protection.outlook.com [IPv6:2a01:111:f400:7eab::615]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AB11A6C1BB; Sat, 11 Mar 2023 16:47:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=KO6BiT2HZSUxZ6bnGoO41T4uSqzazFal1MXQPGXS7z3SwUf3frh/Ky9BZM1iHRuzML2+uRn3/fCb5pUM6ceEu8gVizH2CQJzIHRo956G+fQsbJZt1JMWeFaiUgkyYO6W/SlX70x2xmb1xaEqg2kTpOKrm76HRdzsqbeaWpLj8Ze8f6eWTbmglf3t6H8byylGyfslIyoOmSPwuN7RJHpBFPx7tap7EGWlANnXXIORn4zgjnjfW8khPn6+8Y/5U+QWKj7zKTVHWNxndTTXHxojEiCqvKKp2gWYGsTXjTITBUBOiEo5EB9hZ3wL58kltTQGI6TF+a87GTu7agwLtEW8Yg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=w/oYrqJ2MVHAPXs4YEdRHbzeuMzFW5jeOoSN8M0D6iw=; b=GJHTVXTEKmhMYYnYRUurJfKaqcAFnlOo8jKKnucfyypAC3zVRDaYRTGMxR4wDYVgTPHtWR2qf3HVq6yNVsBumSpSCIZPpMSyb7/YkulG/tUgk1q6sedfXuDrAiCUTVA1rZ1N7SKdflwloDZKeeQKXFEyz15MlN28J7ASBRrcJrp7ZBHVaSXxxCpSGwQlHIcjg6UwAFfpTAa85X2rCXapacSXuXvKfAUy5HLGDocBS+DKAkyO9VKx6SbcXmWcEvuJwx9DjBlM8X2jZyjZ23Jc5cVIBw7awqgrtR278t/Nn7aEvuB1iBflSFfmSPCNQxL4FpU15cTOHRlLB7/Odw1FIg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.infradead.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=w/oYrqJ2MVHAPXs4YEdRHbzeuMzFW5jeOoSN8M0D6iw=; b=ligK2XiryWwl98gmWc70I1jFpFRcluF9nLIsAvlXCejI5n+iThCOYHUVdWO/aHVzDIbBEoM++wGMEePIsfIC7IUh20yRmqeAYeUATleaDIQi+I6VB0bmT+qkpMB7kofFwTMor1idCT2Y3eclDYjYyQyaxjIaOqdrbFbhILvRb+c= Received: from DS7PR05CA0003.namprd05.prod.outlook.com (2603:10b6:5:3b9::8) by CH3PR12MB7546.namprd12.prod.outlook.com (2603:10b6:610:149::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6178.24; Sun, 12 Mar 2023 00:47:08 +0000 Received: from DM6NAM11FT018.eop-nam11.prod.protection.outlook.com (2603:10b6:5:3b9:cafe::3) by DS7PR05CA0003.outlook.office365.com (2603:10b6:5:3b9::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6178.23 via Frontend Transport; Sun, 12 Mar 2023 00:47:08 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT018.mail.protection.outlook.com (10.13.172.110) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6178.18 via Frontend Transport; Sun, 12 Mar 2023 00:47:08 +0000 Received: from platform-dev1.pensando.io (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Sat, 11 Mar 2023 18:47:04 -0600 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v11 13/15] mmc: sdhci-cadence: Add AMD Pensando Elba SoC support Date: Sat, 11 Mar 2023 16:44:43 -0800 Message-ID: <20230312004445.15913-14-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230312004445.15913-1-blarson@amd.com> References: <20230312004445.15913-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT018:EE_|CH3PR12MB7546:EE_ X-MS-Office365-Filtering-Correlation-Id: b3fa9872-e447-4905-d0c9-08db22934eda X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: a0x1WnKBYB1up4RJvbRERridSnZoDqWn1YDzD9/2lSB7M5iU7xQ+gRebvU43tXd7Z5GJLGzM6HIqybY+mgnXlezs57RR7tr1H3RUn/mEQDmCZYinTmMGxGUkcouY8zurml1InPNTxX02vbBmJ2XoTTOw/NNh2+jcPnTHCIyt/IAxqVP3cJh+x9JeXclcosKpZYWe8CGOVb8+XTOzotecHLePk5Bb+5ERz0o/ETd+zlgwk6GqvV8VjnJ1WVDz3LsFIVrqwnBxWO8sps47u6qeCiNhCRAvEiA93PcgyfTaCmUVHM2Ka1EkJjkt5kuuD1RcmgzwrQGxmzdWzvbXPCnBBt5Oy7ZJYoTo/fVNOSwZvEe8DCfHs9KAjhfDGqmOKEiHZUnDPlTZCESlPnUsApXukTalq+pD2L/0d93jiQTywVK4H15l5Vctsm2Lb10ojQTPw4LoJepB6MUpjeNUyqTMAFoImsQ4Jd8CD79sVf9+Ktw9AXYlkiH1PSb5Pg4i9LMGgQx1Gc/pXyiirOxmzbkYkjZPM3dpMxJBmwKpR+PzEE7p6PjgGevMFh+RHSe93/YZuxzvcuEgPqWnNQISAbQ2aBfxKwvZ1oICDsu2QVshg/rC41Ot+1ytRjdp8wCUab81TM6kQgpdJgzJxT4BlVl1wiAgGydffnOyNhRqkWc/MFIdTmOmOveQTpyoMqbLkj6glxukDH/DqjRHKpRzJJkOsH83lGXjKkJNwaktI8XQUqM= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(396003)(136003)(346002)(376002)(39860400002)(451199018)(36840700001)(40470700004)(46966006)(336012)(83380400001)(478600001)(186003)(6666004)(16526019)(26005)(1076003)(70586007)(70206006)(316002)(54906003)(2616005)(426003)(47076005)(8676002)(6916009)(4326008)(41300700001)(36860700001)(8936002)(7406005)(5660300002)(7416002)(81166007)(40460700003)(2906002)(82740400003)(356005)(40480700001)(82310400005)(36756003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Mar 2023 00:47:08.0776 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b3fa9872-e447-4905-d0c9-08db22934eda X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT018.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7546 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,SPF_HELO_PASS, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760121436343869854?= X-GMAIL-MSGID: =?utf-8?q?1760121436343869854?= Add support for AMD Pensando Elba SoC which explicitly controls byte-lane enables on writes. Select MMC_SDHCI_IO_ACCESSORS for MMC_SDHCI_CADENCE which allows Elba SoC sdhci_elba_ops to overwrite the SDHCI IO memory accessors Signed-off-by: Brad Larson Acked-by: Adrian Hunter --- v11 changes: - Remove elba-drv_init() call to platform_get_resource() since that check is done inside devm_platform_ioremap_resource() - Move spin_lock_init() before error check - Remove extra parentheses v10 changes: - Add Elba specific support into this 3rd patch. This builds on the private writel() enabled in patch 1 followed by platform specific init() in patch 2. - Specify when first used the reason for the spinlock use to order byte-enable prior to write data. --- drivers/mmc/host/Kconfig | 1 + drivers/mmc/host/sdhci-cadence.c | 96 ++++++++++++++++++++++++++++++++ 2 files changed, 97 insertions(+) diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 4745fe217ade..9f793892123c 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -255,6 +255,7 @@ config MMC_SDHCI_CADENCE tristate "SDHCI support for the Cadence SD/SDIO/eMMC controller" depends on MMC_SDHCI_PLTFM depends on OF + select MMC_SDHCI_IO_ACCESSORS help This selects the Cadence SD/SDIO/eMMC driver. diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c index c528a25f48b8..c0024d1e69a8 100644 --- a/drivers/mmc/host/sdhci-cadence.c +++ b/drivers/mmc/host/sdhci-cadence.c @@ -66,6 +66,8 @@ struct sdhci_cdns_phy_param { struct sdhci_cdns_priv { void __iomem *hrs_addr; + void __iomem *ctl_addr; /* write control */ + spinlock_t wrlock; /* write lock */ bool enhanced_strobe; void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg); unsigned int nr_phy_params; @@ -321,6 +323,89 @@ static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host, sdhci_set_uhs_signaling(host, timing); } +/* Elba control register bits [6:3] are byte-lane enables */ +#define ELBA_BYTE_ENABLE_MASK(x) ((x) << 3) + +/* + * The Pensando Elba SoC explicitly controls byte-lane enabling on writes + * which includes writes to the HRS registers. The write lock (wrlock) + * is used to ensure byte-lane enable, using write control (ctl_addr), + * occurs before the data write. + */ +static void elba_priv_writel(struct sdhci_cdns_priv *priv, u32 val, + void __iomem *reg) +{ + unsigned long flags; + + spin_lock_irqsave(&priv->wrlock, flags); + writel(ELBA_BYTE_ENABLE_MASK(0xf), priv->ctl_addr); + writel(val, reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static void elba_write_l(struct sdhci_host *host, u32 val, int reg) +{ + elba_priv_writel(sdhci_cdns_priv(host), val, host->ioaddr + reg); +} + +static void elba_write_w(struct sdhci_host *host, u16 val, int reg) +{ + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + u32 byte_enables; + unsigned long flags; + + byte_enables = GENMASK(1, 0) << (reg & 0x3); + spin_lock_irqsave(&priv->wrlock, flags); + writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr); + writew(val, host->ioaddr + reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static void elba_write_b(struct sdhci_host *host, u8 val, int reg) +{ + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + u32 byte_enables; + unsigned long flags; + + byte_enables = BIT(0) << (reg & 0x3); + spin_lock_irqsave(&priv->wrlock, flags); + writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr); + writeb(val, host->ioaddr + reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static const struct sdhci_ops sdhci_elba_ops = { + .write_l = elba_write_l, + .write_w = elba_write_w, + .write_b = elba_write_b, + .set_clock = sdhci_set_clock, + .get_timeout_clock = sdhci_cdns_get_timeout_clock, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_cdns_set_uhs_signaling, +}; + +static int elba_drv_init(struct platform_device *pdev) +{ + struct sdhci_host *host = platform_get_drvdata(pdev); + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + void __iomem *ioaddr; + + host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA; + spin_lock_init(&priv->wrlock); + + /* Byte-lane control register */ + ioaddr = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(ioaddr)) + return PTR_ERR(ioaddr); + + priv->ctl_addr = ioaddr; + priv->priv_writel = elba_priv_writel; + writel(ELBA_BYTE_ENABLE_MASK(0xf), priv->ctl_addr); + + return 0; +} + static const struct sdhci_ops sdhci_cdns_ops = { .set_clock = sdhci_set_clock, .get_timeout_clock = sdhci_cdns_get_timeout_clock, @@ -337,6 +422,13 @@ static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data = { }, }; +static const struct sdhci_cdns_drv_data sdhci_elba_drv_data = { + .init = elba_drv_init, + .pltfm_data = { + .ops = &sdhci_elba_ops, + }, +}; + static const struct sdhci_cdns_drv_data sdhci_cdns_drv_data = { .pltfm_data = { .ops = &sdhci_cdns_ops, @@ -477,6 +569,10 @@ static const struct of_device_id sdhci_cdns_match[] = { .compatible = "socionext,uniphier-sd4hc", .data = &sdhci_cdns_uniphier_drv_data, }, + { + .compatible = "amd,pensando-elba-sd4hc", + .data = &sdhci_elba_drv_data, + }, { .compatible = "cdns,sd4hc" }, { /* sentinel */ } };