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Sat, 11 Mar 2023 18:46:22 -0600 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v11 10/15] spi: dw: Add support for AMD Pensando Elba SoC Date: Sat, 11 Mar 2023 16:44:40 -0800 Message-ID: <20230312004445.15913-11-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230312004445.15913-1-blarson@amd.com> References: <20230312004445.15913-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT062:EE_|IA0PR12MB7628:EE_ X-MS-Office365-Filtering-Correlation-Id: 44549a0f-6b68-47a2-0aa7-08db22933643 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: d+1Z/dLwKZWGZ21UJFg2plJLnH6rxzQKEqRn58K8Fu/APSJ9eQLGfbFNBbEXwLU4efPHOb/GFgBqTtySxJd2b0+I5caCQwgRthHgRXukojEBLoPC0UnEYLT6+3br2cY7vOOsLNRsqPdGG6Ev741Fg7V0b8gqzbVgShq5yapwDgLWXz9sXyRlaqo5ofxYmTeGbVYc/OObAOyZI3n6jjS8VT0iJcvuZHZgG/Z5UDqMhjFeB5iBZS6mSjHca2jDZEbaYBQUDMaC3wXde0JNcvbWOYOGrRoWIqxoSZBYGM1QuETiKhvAPKWG1UloQzOGzs5qCVKgy/pKJ5ICxop7i/xLT75IYh6cld/EyWLlZBrKq3NQFA6riftPHJPEGmjdrk8zKBVY+EhAWjVZoIxiskbHrsK/ZgCXkTe26KeT99tPtOroL3QfZMzY+XRLnARz9y6R4pesu0/sNX3cdHlP6aidHuNNXWQAnK7nRVRLiV3nZssx6AWT+pZoWsO2E/3PL7j60LR1CjGMzOGWdzCKSSdTzZFQnM26SvUk+7VtyPVEHBPOSOVAsAK1y83MuhJV0gBmWJaOdLe2uV8AELu+lFX7UAaMOq0GIy4bNALW9Sdw+r2xHOHV9NOhEyESURQ9R3A38VuCnSEQGku72ry8/6CHmG/SzrGM0J0RCWKsZONS8rx1wccMGUpSgRDbOO4Yj3OdCLuqm7WxIJKl6N01uSN+YMSmiz+OzcDDhiftbQT+deQ= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(376002)(136003)(39860400002)(396003)(346002)(451199018)(36840700001)(46966006)(40470700004)(8676002)(4326008)(6916009)(70586007)(70206006)(83380400001)(5660300002)(41300700001)(316002)(36860700001)(54906003)(2616005)(8936002)(47076005)(2906002)(36756003)(478600001)(82740400003)(7406005)(426003)(7416002)(40460700003)(40480700001)(81166007)(82310400005)(336012)(356005)(6666004)(186003)(16526019)(26005)(1076003)(36900700001);DIR:OUT;SFP:1101; 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The Elba SoC provides four chip-selects where the native DW IP supports two chip-selects. The Elba DW_SPI instance has two native CS signals that are always overridden. Signed-off-by: Brad Larson Reviewed-by: Serge Semin --- v11 changes: - Simplify dw_spi_elb_init by using syscon_regmap_lookup_by_phandle() v10 changes: - Delete struct dw_spi_elba, use regmap directly in priv v9 changes: - Add use of macros GENMASK() and BIT() - Change ELBA_SPICS_SHIFT() to ELBA_SPICS_OFFSET() --- drivers/spi/spi-dw-mmio.c | 57 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index 26c40ea6dd12..5851ecc6e1e9 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -53,6 +53,20 @@ struct dw_spi_mscc { void __iomem *spi_mst; /* Not sparx5 */ }; +/* + * Elba SoC does not use ssi, pin override is used for cs 0,1 and + * gpios for cs 2,3 as defined in the device tree. + * + * cs: | 1 0 + * bit: |---3-------2-------1-------0 + * | cs1 cs1_ovr cs0 cs0_ovr + */ +#define ELBA_SPICS_REG 0x2468 +#define ELBA_SPICS_OFFSET(cs) ((cs) << 1) +#define ELBA_SPICS_MASK(cs) (GENMASK(1, 0) << ELBA_SPICS_OFFSET(cs)) +#define ELBA_SPICS_SET(cs, val) \ + ((((val) << 1) | BIT(0)) << ELBA_SPICS_OFFSET(cs)) + /* * The Designware SPI controller (referred to as master in the documentation) * automatically deasserts chip select when the tx fifo is empty. The chip @@ -237,6 +251,48 @@ static int dw_spi_canaan_k210_init(struct platform_device *pdev, return 0; } +static void dw_spi_elba_override_cs(struct regmap *syscon, int cs, int enable) +{ + regmap_update_bits(syscon, ELBA_SPICS_REG, ELBA_SPICS_MASK(cs), + ELBA_SPICS_SET(cs, enable)); +} + +static void dw_spi_elba_set_cs(struct spi_device *spi, bool enable) +{ + struct dw_spi *dws = spi_master_get_devdata(spi->master); + struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws); + struct regmap *syscon = dwsmmio->priv; + u8 cs; + + cs = spi->chip_select; + if (cs < 2) + dw_spi_elba_override_cs(syscon, spi->chip_select, enable); + + /* + * The DW SPI controller needs a native CS bit selected to start + * the serial engine. + */ + spi->chip_select = 0; + dw_spi_set_cs(spi, enable); + spi->chip_select = cs; +} + +static int dw_spi_elba_init(struct platform_device *pdev, + struct dw_spi_mmio *dwsmmio) +{ + struct regmap *syscon; + + syscon = syscon_regmap_lookup_by_phandle(dev_of_node(&pdev->dev), + "amd,pensando-elba-syscon"); + if (IS_ERR(syscon)) + return dev_err_probe(&pdev->dev, PTR_ERR(syscon), + "syscon regmap lookup failed\n"); + dwsmmio->priv = syscon; + dwsmmio->dws.set_cs = dw_spi_elba_set_cs; + + return 0; +} + static int dw_spi_mmio_probe(struct platform_device *pdev) { int (*init_func)(struct platform_device *pdev, @@ -352,6 +408,7 @@ static const struct of_device_id dw_spi_mmio_of_match[] = { { .compatible = "intel,thunderbay-ssi", .data = dw_spi_intel_init}, { .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init}, { .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init}, + { .compatible = "amd,pensando-elba-spi", .data = dw_spi_elba_init}, { /* end of table */} }; MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);