diff mbox series

[v5,06/21] reset: Create subdirectory for StarFive drivers

Message ID	20230311090733.56918-7-hal.feng@starfivetech.com
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; From: Hal Feng <hal.feng@starfivetech.com> To: <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org> CC: Stephen Boyd <sboyd@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Philipp Zabel <p.zabel@pengutronix.de>, "Rob Herring" <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor@kernel.org>, "Palmer Dabbelt" <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Ben Dooks <ben.dooks@sifive.com>, "Daniel Lezcano" <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Emil Renner Berthing <emil.renner.berthing@canonical.com>, Hal Feng <hal.feng@starfivetech.com>, <linux-kernel@vger.kernel.org> Subject: [PATCH v5 06/21] reset: Create subdirectory for StarFive drivers Date: Sat, 11 Mar 2023 17:07:18 +0800 Message-ID: <20230311090733.56918-7-hal.feng@starfivetech.com> In-Reply-To: <20230311090733.56918-1-hal.feng@starfivetech.com> References: <20230311090733.56918-1-hal.feng@starfivetech.com> MIME-Version: 1.0 Content-Type: text/plain Content-Transfer-Encoding: 8BIT Precedence: bulk
Series	Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC \| [v5,00/21] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC [v5,01/21] clk: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE [v5,02/21] clk: starfive: Factor out common JH7100 and JH7110 code [v5,03/21] clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h [v5,04/21] clk: starfive: Rename "jh7100" to "jh71x0" for the common code [v5,05/21] reset: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE [v5,06/21] reset: Create subdirectory for StarFive drivers [v5,07/21] reset: starfive: Factor out common JH71X0 reset code [v5,08/21] reset: starfive: Extract the common JH71X0 reset code [v5,09/21] reset: starfive: Rename "jh7100" to "jh71x0" for the common code [v5,10/21] reset: starfive: jh71x0: Use 32bit I/O on 32bit registers [v5,11/21] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator [v5,12/21] dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator [v5,13/21] clk: starfive: Add StarFive JH7110 system clock driver [v5,14/21] clk: starfive: Add StarFive JH7110 always-on clock driver [v5,15/21] reset: starfive: Add StarFive JH7110 reset driver [v5,16/21] dt-bindings: timer: Add StarFive JH7110 clint [v5,17/21] dt-bindings: interrupt-controller: Add StarFive JH7110 plic [v5,18/21] dt-bindings: riscv: Add SiFive S7 compatible [v5,19/21] riscv: dts: starfive: Add initial StarFive JH7110 device tree [v5,20/21] riscv: dts: starfive: Add StarFive JH7110 pin function definitions [v5,21/21] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree

Commit Message

Hal Feng March 11, 2023, 9:07 a.m. UTC

  From: Emil Renner Berthing <kernel@esmil.dk>

This moves the StarFive JH7100 reset driver to a new subdirectory in
preparation for adding more StarFive reset drivers.

Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
 MAINTAINERS                                          | 2 +-
 drivers/reset/Kconfig                                | 8 +-------
 drivers/reset/Makefile                               | 2 +-
 drivers/reset/starfive/Kconfig                       | 8 ++++++++
 drivers/reset/starfive/Makefile                      | 2 ++
 drivers/reset/{ => starfive}/reset-starfive-jh7100.c | 0
 6 files changed, 13 insertions(+), 9 deletions(-)
 create mode 100644 drivers/reset/starfive/Kconfig
 create mode 100644 drivers/reset/starfive/Makefile
 rename drivers/reset/{ => starfive}/reset-starfive-jh7100.c (100%)

Comments

Philipp Zabel March 14, 2023, 2:34 p.m. UTC | #1

On Sa, 2023-03-11 at 17:07 +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
> 
> This moves the StarFive JH7100 reset driver to a new subdirectory in
> preparation for adding more StarFive reset drivers.
> 
> Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
>  MAINTAINERS                                          | 2 +-
>  drivers/reset/Kconfig                                | 8 +-------
>  drivers/reset/Makefile                               | 2 +-
>  drivers/reset/starfive/Kconfig                       | 8 ++++++++
>  drivers/reset/starfive/Makefile                      | 2 ++
>  drivers/reset/{ => starfive}/reset-starfive-jh7100.c | 0
>  6 files changed, 13 insertions(+), 9 deletions(-)
>  create mode 100644 drivers/reset/starfive/Kconfig
>  create mode 100644 drivers/reset/starfive/Makefile
>  rename drivers/reset/{ => starfive}/reset-starfive-jh7100.c (100%)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index caba3b61ad5c..87f210e357ca 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -19940,7 +19940,7 @@ STARFIVE JH7100 RESET CONTROLLER DRIVER
>  M:	Emil Renner Berthing <kernel@esmil.dk>
>  S:	Maintained
>  F:	Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
> -F:	drivers/reset/reset-starfive-jh7100.c
> +F:	drivers/reset/starfive/reset-starfive-jh7100.c
>  F:	include/dt-bindings/reset/starfive-jh7100.h
>  
> 
> 
> 
>  STARFIVE JH71XX PMU CONTROLLER DRIVER
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index 6ae5aa46a6b2..6aa8f243b30c 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -232,13 +232,6 @@ config RESET_SOCFPGA
>  	  This enables the reset driver for the SoCFPGA ARMv7 platforms. This
>  	  driver gets initialized early during platform init calls.
>  
> 
> 
> 
> -config RESET_STARFIVE_JH7100
> -	bool "StarFive JH7100 Reset Driver"
> -	depends on ARCH_STARFIVE || COMPILE_TEST
> -	default ARCH_STARFIVE
> -	help
> -	  This enables the reset controller driver for the StarFive JH7100 SoC.
> -
>  config RESET_SUNPLUS
>  	bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
>  	default ARCH_SUNPLUS
> @@ -320,6 +313,7 @@ config RESET_ZYNQ
>  	help
>  	  This enables the reset controller driver for Xilinx Zynq SoCs.
>  
> 
> 
> 
> +source "drivers/reset/starfive/Kconfig"
>  source "drivers/reset/sti/Kconfig"
>  source "drivers/reset/hisilicon/Kconfig"
>  source "drivers/reset/tegra/Kconfig"
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index 3e7e5fd633a8..719b8f6f84bc 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -1,6 +1,7 @@
>  # SPDX-License-Identifier: GPL-2.0
>  obj-y += core.o
>  obj-y += hisilicon/
> +obj-$(CONFIG_ARCH_STARFIVE) += starfive/

This should really be obj-y, otherwise this won't compile with
COMPILE_TEST=y but ARCH_STARFIVE=n.

With that fixed,
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>

regards
Philipp

Hal Feng March 17, 2023, 8:17 a.m. UTC | #2

On Tue, 14 Mar 2023 15:34:26 +0100, Philipp Zabel wrote:
> On Sa, 2023-03-11 at 17:07 +0800, Hal Feng wrote:
>> From: Emil Renner Berthing <kernel@esmil.dk>
>> 
>> This moves the StarFive JH7100 reset driver to a new subdirectory in
>> preparation for adding more StarFive reset drivers.
>> 
>> Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
>> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
>> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>> ---
>>  MAINTAINERS                                          | 2 +-
>>  drivers/reset/Kconfig                                | 8 +-------
>>  drivers/reset/Makefile                               | 2 +-
>>  drivers/reset/starfive/Kconfig                       | 8 ++++++++
>>  drivers/reset/starfive/Makefile                      | 2 ++
>>  drivers/reset/{ => starfive}/reset-starfive-jh7100.c | 0
>>  6 files changed, 13 insertions(+), 9 deletions(-)
>>  create mode 100644 drivers/reset/starfive/Kconfig
>>  create mode 100644 drivers/reset/starfive/Makefile
>>  rename drivers/reset/{ => starfive}/reset-starfive-jh7100.c (100%)
>> 
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index caba3b61ad5c..87f210e357ca 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -19940,7 +19940,7 @@ STARFIVE JH7100 RESET CONTROLLER DRIVER
>>  M:	Emil Renner Berthing <kernel@esmil.dk>
>>  S:	Maintained
>>  F:	Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
>> -F:	drivers/reset/reset-starfive-jh7100.c
>> +F:	drivers/reset/starfive/reset-starfive-jh7100.c
>>  F:	include/dt-bindings/reset/starfive-jh7100.h
>>  
>> 
>> 
>> 
>>  STARFIVE JH71XX PMU CONTROLLER DRIVER
>> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
>> index 6ae5aa46a6b2..6aa8f243b30c 100644
>> --- a/drivers/reset/Kconfig
>> +++ b/drivers/reset/Kconfig
>> @@ -232,13 +232,6 @@ config RESET_SOCFPGA
>>  	  This enables the reset driver for the SoCFPGA ARMv7 platforms. This
>>  	  driver gets initialized early during platform init calls.
>>  
>> 
>> 
>> 
>> -config RESET_STARFIVE_JH7100
>> -	bool "StarFive JH7100 Reset Driver"
>> -	depends on ARCH_STARFIVE || COMPILE_TEST
>> -	default ARCH_STARFIVE
>> -	help
>> -	  This enables the reset controller driver for the StarFive JH7100 SoC.
>> -
>>  config RESET_SUNPLUS
>>  	bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
>>  	default ARCH_SUNPLUS
>> @@ -320,6 +313,7 @@ config RESET_ZYNQ
>>  	help
>>  	  This enables the reset controller driver for Xilinx Zynq SoCs.
>>  
>> 
>> 
>> 
>> +source "drivers/reset/starfive/Kconfig"
>>  source "drivers/reset/sti/Kconfig"
>>  source "drivers/reset/hisilicon/Kconfig"
>>  source "drivers/reset/tegra/Kconfig"
>> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
>> index 3e7e5fd633a8..719b8f6f84bc 100644
>> --- a/drivers/reset/Makefile
>> +++ b/drivers/reset/Makefile
>> @@ -1,6 +1,7 @@
>>  # SPDX-License-Identifier: GPL-2.0
>>  obj-y += core.o
>>  obj-y += hisilicon/
>> +obj-$(CONFIG_ARCH_STARFIVE) += starfive/
> 
> This should really be obj-y, otherwise this won't compile with
> COMPILE_TEST=y but ARCH_STARFIVE=n.
> 
> With that fixed,
> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>

The same problem exists in drivers/clk/Makefile.
Will fix them in the next version. Thank you for your review.

Best regards,
Hal

diff mbox series

Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index caba3b61ad5c..87f210e357ca 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19940,7 +19940,7 @@  STARFIVE JH7100 RESET CONTROLLER DRIVER
 M:	Emil Renner Berthing <kernel@esmil.dk>
 S:	Maintained
 F:	Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
-F:	drivers/reset/reset-starfive-jh7100.c
+F:	drivers/reset/starfive/reset-starfive-jh7100.c
 F:	include/dt-bindings/reset/starfive-jh7100.h
 
 STARFIVE JH71XX PMU CONTROLLER DRIVER
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 6ae5aa46a6b2..6aa8f243b30c 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -232,13 +232,6 @@  config RESET_SOCFPGA
 	  This enables the reset driver for the SoCFPGA ARMv7 platforms. This
 	  driver gets initialized early during platform init calls.
 
-config RESET_STARFIVE_JH7100
-	bool "StarFive JH7100 Reset Driver"
-	depends on ARCH_STARFIVE || COMPILE_TEST
-	default ARCH_STARFIVE
-	help
-	  This enables the reset controller driver for the StarFive JH7100 SoC.
-
 config RESET_SUNPLUS
 	bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
 	default ARCH_SUNPLUS
@@ -320,6 +313,7 @@  config RESET_ZYNQ
 	help
 	  This enables the reset controller driver for Xilinx Zynq SoCs.
 
+source "drivers/reset/starfive/Kconfig"
 source "drivers/reset/sti/Kconfig"
 source "drivers/reset/hisilicon/Kconfig"
 source "drivers/reset/tegra/Kconfig"
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 3e7e5fd633a8..719b8f6f84bc 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -1,6 +1,7 @@ 
 # SPDX-License-Identifier: GPL-2.0
 obj-y += core.o
 obj-y += hisilicon/
+obj-$(CONFIG_ARCH_STARFIVE) += starfive/
 obj-$(CONFIG_ARCH_STI) += sti/
 obj-$(CONFIG_ARCH_TEGRA) += tegra/
 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
@@ -30,7 +31,6 @@  obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o
 obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
 obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
 obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
-obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
 obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o
 obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
 obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
diff --git a/drivers/reset/starfive/Kconfig b/drivers/reset/starfive/Kconfig
new file mode 100644
index 000000000000..abbf0c52d03e
--- /dev/null
+++ b/drivers/reset/starfive/Kconfig
@@ -0,0 +1,8 @@ 
+# SPDX-License-Identifier: GPL-2.0-only
+
+config RESET_STARFIVE_JH7100
+	bool "StarFive JH7100 Reset Driver"
+	depends on ARCH_STARFIVE || COMPILE_TEST
+	default ARCH_STARFIVE
+	help
+	  This enables the reset controller driver for the StarFive JH7100 SoC.
diff --git a/drivers/reset/starfive/Makefile b/drivers/reset/starfive/Makefile
new file mode 100644
index 000000000000..670d049423f5
--- /dev/null
+++ b/drivers/reset/starfive/Makefile
@@ -0,0 +1,2 @@ 
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_RESET_STARFIVE_JH7100)		+= reset-starfive-jh7100.o
diff --git a/drivers/reset/reset-starfive-jh7100.c b/drivers/reset/starfive/reset-starfive-jh7100.c
similarity index 100%
rename from drivers/reset/reset-starfive-jh7100.c
rename to drivers/reset/starfive/reset-starfive-jh7100.c