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[v5,18/21] dt-bindings: riscv: Add SiFive S7 compatible

Message ID	20230311090733.56918-19-hal.feng@starfivetech.com
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; From: Hal Feng <hal.feng@starfivetech.com> To: <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org> CC: Stephen Boyd <sboyd@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Philipp Zabel <p.zabel@pengutronix.de>, "Rob Herring" <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor@kernel.org>, "Palmer Dabbelt" <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Ben Dooks <ben.dooks@sifive.com>, "Daniel Lezcano" <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Emil Renner Berthing <emil.renner.berthing@canonical.com>, Hal Feng <hal.feng@starfivetech.com>, <linux-kernel@vger.kernel.org> Subject: [PATCH v5 18/21] dt-bindings: riscv: Add SiFive S7 compatible Date: Sat, 11 Mar 2023 17:07:30 +0800 Message-ID: <20230311090733.56918-19-hal.feng@starfivetech.com> In-Reply-To: <20230311090733.56918-1-hal.feng@starfivetech.com> References: <20230311090733.56918-1-hal.feng@starfivetech.com> MIME-Version: 1.0 Content-Type: text/plain Content-Transfer-Encoding: 8BIT Precedence: bulk
Series	Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC \| [v5,00/21] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC [v5,01/21] clk: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE [v5,02/21] clk: starfive: Factor out common JH7100 and JH7110 code [v5,03/21] clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h [v5,04/21] clk: starfive: Rename "jh7100" to "jh71x0" for the common code [v5,05/21] reset: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE [v5,06/21] reset: Create subdirectory for StarFive drivers [v5,07/21] reset: starfive: Factor out common JH71X0 reset code [v5,08/21] reset: starfive: Extract the common JH71X0 reset code [v5,09/21] reset: starfive: Rename "jh7100" to "jh71x0" for the common code [v5,10/21] reset: starfive: jh71x0: Use 32bit I/O on 32bit registers [v5,11/21] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator [v5,12/21] dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator [v5,13/21] clk: starfive: Add StarFive JH7110 system clock driver [v5,14/21] clk: starfive: Add StarFive JH7110 always-on clock driver [v5,15/21] reset: starfive: Add StarFive JH7110 reset driver [v5,16/21] dt-bindings: timer: Add StarFive JH7110 clint [v5,17/21] dt-bindings: interrupt-controller: Add StarFive JH7110 plic [v5,18/21] dt-bindings: riscv: Add SiFive S7 compatible [v5,19/21] riscv: dts: starfive: Add initial StarFive JH7110 device tree [v5,20/21] riscv: dts: starfive: Add StarFive JH7110 pin function definitions [v5,21/21] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree

Commit Message

Hal Feng March 11, 2023, 9:07 a.m. UTC

  Add a new compatible string in cpu.yaml for SiFive S7 CPU
core which is used on SiFive U74-MC core complex etc.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

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Patch

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 001931d526ec..14b5b7ea0ce0 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -35,6 +35,7 @@  properties:
               - sifive,e7
               - sifive,e71
               - sifive,rocket0
+              - sifive,s7
               - sifive,u5
               - sifive,u54
               - sifive,u7