@@ -235,7 +235,7 @@ int __init btext_find_display(int allow_nonstdout)
return rc;
for_each_node_by_type(np, "display") {
- if (of_get_property(np, "linux,opened", NULL)) {
+ if (of_property_read_bool(np, "linux,opened")) {
printk("trying %pOF ...\n", np);
rc = btext_initialize(np);
printk("result: %d\n", rc);
@@ -179,7 +179,7 @@ static int __init add_legacy_soc_port(struct device_node *np,
return -1;
/* if rtas uses this device, don't try to use it as well */
- if (of_get_property(np, "used-by-rtas", NULL) != NULL)
+ if (of_property_read_bool(np, "used-by-rtas"))
return -1;
/* Get the address */
@@ -348,7 +348,7 @@ static void __init ppc4xx_probe_pci_bridge(struct device_node *np)
}
/* Check if primary bridge */
- if (of_property_present(np, "primary"))
+ if (of_property_read_bool(np, "primary"))
primary = 1;
/* Get bus range if any */
@@ -530,7 +530,7 @@ static void __init ppc4xx_probe_pcix_bridge(struct device_node *np)
struct pci_controller *hose = NULL;
void __iomem *reg = NULL;
const int *bus_range;
- int big_pim = 0, msi = 0, primary = 0;
+ int big_pim, msi, primary;
/* Fetch config space registers address */
if (of_address_to_resource(np, 0, &rsrc_cfg)) {
@@ -546,16 +546,13 @@ static void __init ppc4xx_probe_pcix_bridge(struct device_node *np)
}
/* Check if it supports large PIMs (440GX) */
- if (of_get_property(np, "large-inbound-windows", NULL))
- big_pim = 1;
+ big_pim = of_property_read_bool(np, "large-inbound-windows");
/* Check if we should enable MSIs inbound hole */
- if (of_get_property(np, "enable-msi-hole", NULL))
- msi = 1;
+ msi = of_property_read_bool(np, "enable-msi-hole");
/* Check if primary bridge */
- if (of_get_property(np, "primary", NULL))
- primary = 1;
+ primary = of_property_read_bool(np, "primary");
/* Get bus range if any */
bus_range = of_get_property(np, "bus-range", NULL);
@@ -1915,14 +1912,13 @@ static void __init ppc4xx_pciex_port_setup_hose(struct ppc4xx_pciex_port *port)
struct resource dma_window;
struct pci_controller *hose = NULL;
const int *bus_range;
- int primary = 0, busses;
+ int primary, busses;
void __iomem *mbase = NULL, *cfg_data = NULL;
const u32 *pval;
u32 val;
/* Check if primary bridge */
- if (of_get_property(port->node, "primary", NULL))
- primary = 1;
+ primary = of_property_read_bool(port->node, "primary");
/* Get bus range if any */
bus_range = of_get_property(port->node, "bus-range", NULL);
@@ -141,8 +141,8 @@ mpc52xx_map_common_devices(void)
* on a gpt0, so check has-wdt property before mapping.
*/
for_each_matching_node(np, mpc52xx_gpt_ids) {
- if (of_get_property(np, "fsl,has-wdt", NULL) ||
- of_get_property(np, "has-wdt", NULL)) {
+ if (of_property_read_bool(np, "fsl,has-wdt") ||
+ of_property_read_bool(np, "has-wdt")) {
mpc52xx_wdt = of_iomap(np, 0);
of_node_put(np);
break;
@@ -735,8 +735,8 @@ static int mpc52xx_gpt_probe(struct platform_device *ofdev)
mutex_unlock(&mpc52xx_gpt_list_mutex);
/* check if this device could be a watchdog */
- if (of_get_property(ofdev->dev.of_node, "fsl,has-wdt", NULL) ||
- of_get_property(ofdev->dev.of_node, "has-wdt", NULL)) {
+ if (of_property_read_bool(ofdev->dev.of_node, "fsl,has-wdt") ||
+ of_property_read_bool(ofdev->dev.of_node, "has-wdt")) {
const u32 *on_boot_wdt;
gpt->wdt_mode = MPC52xx_GPT_CAN_WDT;
@@ -235,7 +235,7 @@ static void __init maple_init_IRQ(void)
BUG_ON(openpic_addr == 0);
/* Check for a big endian MPIC */
- if (of_get_property(np, "big-endian", NULL) != NULL)
+ if (of_property_read_bool(np, "big-endian"))
flags |= MPIC_BIG_ENDIAN;
/* XXX Maple specific bits */
@@ -254,7 +254,7 @@ void __init iommu_init_early_pasemi(void)
iommu_off = 1;
#else
iommu_off = of_chosen &&
- of_get_property(of_chosen, "linux,iommu-off", NULL);
+ of_property_read_bool(of_chosen, "linux,iommu-off");
#endif
if (iommu_off)
return;
@@ -2506,7 +2506,7 @@ static int __init probe_motherboard(void)
int cpu_count = 1;
/* Nap mode not supported on SMP */
- if (of_get_property(np, "flush-on-lock", NULL) ||
+ if (of_property_read_bool(np, "flush-on-lock") ||
(cpu_count > 1)) {
powersave_nap = 0;
of_node_put(np);
@@ -450,7 +450,7 @@ static struct mpic * __init pmac_setup_one_mpic(struct device_node *np,
pmac_call_feature(PMAC_FTR_ENABLE_MPIC, np, 0, 0);
- if (of_get_property(np, "big-endian", NULL))
+ if (of_property_read_bool(np, "big-endian"))
flags |= MPIC_BIG_ENDIAN;
/* Primary Big Endian means HT interrupts. This is quite dodgy
@@ -528,7 +528,7 @@ void __init pmac_pic_init(void)
#ifdef CONFIG_PPC32
if (!pmac_newworld)
of_irq_workarounds |= OF_IMAP_OLDWORLD_MAC;
- if (of_get_property(of_chosen, "linux,bootx", NULL) != NULL)
+ if (of_property_read_bool(of_chosen, "linux,bootx"))
of_irq_workarounds |= OF_IMAP_NO_PHANDLE;
/* If we don't have phandles on a newworld, then try to locate a
@@ -137,7 +137,7 @@ static void pmac_show_cpuinfo(struct seq_file *m)
of_get_property(np, "d-cache-size", NULL);
seq_printf(m, "L2 cache\t:");
has_l2cache = 1;
- if (of_get_property(np, "cache-unified", NULL) && dc) {
+ if (of_property_read_bool(np, "cache-unified") && dc) {
seq_printf(m, " %dK unified", *dc / 1024);
} else {
if (ic)
@@ -706,7 +706,7 @@ static void __init smp_core99_setup(int ncpus)
struct device_node *cpus =
of_find_node_by_path("/cpus");
if (cpus &&
- of_get_property(cpus, "platform-cpu-timebase", NULL)) {
+ of_property_read_bool(cpus, "platform-cpu-timebase")) {
pmac_tb_freeze = smp_core99_pfunc_tb_freeze;
printk(KERN_INFO "Processor timebase sync using"
" platform function\n");
@@ -1381,7 +1381,7 @@ struct vio_dev *vio_register_device_node(struct device_node *of_node)
}
if (family == PFO) {
- if (of_get_property(of_node, "interrupt-controller", NULL)) {
+ if (of_property_read_bool(of_node, "interrupt-controller")) {
pr_debug("%s: Skipping the interrupt controller %pOFn.\n",
__func__, of_node);
return NULL;
@@ -18,7 +18,7 @@ static struct device_node *find_dcr_parent(struct device_node *node)
const u32 *p;
for (par = of_node_get(node); par;) {
- if (of_get_property(par, "dcr-controller", NULL))
+ if (of_property_read_bool(par, "dcr-controller"))
break;
p = of_get_property(par, "dcr-parent", NULL);
tmp = par;
@@ -256,7 +256,6 @@ void __init ehv_pic_init(void)
{
struct device_node *np, *np2;
struct ehv_pic *ehv_pic;
- int coreint_flag = 1;
np = of_find_compatible_node(NULL, NULL, "epapr,hv-pic");
if (!np) {
@@ -264,9 +263,6 @@ void __init ehv_pic_init(void)
return;
}
- if (!of_find_property(np, "has-external-proxy", NULL))
- coreint_flag = 0;
-
ehv_pic = kzalloc(sizeof(struct ehv_pic), GFP_KERNEL);
if (!ehv_pic) {
of_node_put(np);
@@ -292,7 +288,7 @@ void __init ehv_pic_init(void)
ehv_pic->hc_irq = ehv_pic_irq_chip;
ehv_pic->hc_irq.irq_set_affinity = ehv_pic_set_affinity;
- ehv_pic->coreint_flag = coreint_flag;
+ ehv_pic->coreint_flag = of_property_read_bool(np, "has-external-proxy");
global_ehv_pic = ehv_pic;
irq_set_default_host(global_ehv_pic->irqhost);
@@ -174,7 +174,7 @@ static int __init setup_rstcr(void)
};
for_each_node_by_name(np, "global-utilities") {
- if ((of_get_property(np, "fsl,has-rstcr", NULL))) {
+ if (of_property_read_bool(np, "fsl,has-rstcr")) {
rstcr = of_iomap(np, 0) + 0xb0;
if (!rstcr) {
printk (KERN_ERR "Error: reset control "
@@ -1260,11 +1260,11 @@ struct mpic * __init mpic_alloc(struct device_node *node,
}
/* Read extra device-tree properties into the flags variable */
- if (of_get_property(node, "big-endian", NULL))
+ if (of_property_read_bool(node, "big-endian"))
flags |= MPIC_BIG_ENDIAN;
- if (of_get_property(node, "pic-no-reset", NULL))
+ if (of_property_read_bool(node, "pic-no-reset"))
flags |= MPIC_NO_RESET;
- if (of_get_property(node, "single-cpu-affinity", NULL))
+ if (of_property_read_bool(node, "single-cpu-affinity"))
flags |= MPIC_SINGLE_DEST_CPU;
if (of_device_is_compatible(node, "fsl,mpic")) {
flags |= MPIC_FSL | MPIC_LARGE_VECTORS;
@@ -132,7 +132,7 @@ static int __init tsi108_eth_of_init(void)
* driver itself to phylib and use a non-misleading
* name for the workaround flag - it's not actually to
* do with the model of PHY in use */
- if (of_get_property(phy, "txc-rxc-delay-disable", NULL))
+ if (of_property_read_bool(phy, "txc-rxc-delay-disable"))
tsi_eth_data.phy_type = TSI108_PHY_BCM54XX;
of_node_put(phy);
@@ -599,11 +599,9 @@ bool __init xive_native_init(void)
}
/* Do we support single escalation */
- if (of_get_property(np, "single-escalation-support", NULL) != NULL)
- xive_has_single_esc = true;
+ xive_has_single_esc = of_property_read_bool(np, "single-escalation-support");
- if (of_get_property(np, "vp-save-restore", NULL))
- xive_has_save_restore = true;
+ xive_has_save_restore = of_property_read_bool(np, "vp-save-restore");
/* Configure Thread Management areas for KVM */
for_each_possible_cpu(cpu)