From patchwork Fri Mar 10 09:45:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Ghiti X-Patchwork-Id: 67314 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp780083wrd; Fri, 10 Mar 2023 01:58:52 -0800 (PST) X-Google-Smtp-Source: AK7set9kr2fHIRxLgRHwodTCtzo4iziIsNioJprHioAzjZkdGKrceYwFnaKr93XaKHHf9ttZR+ta X-Received: by 2002:a05:6a20:7d9e:b0:cd:8ed8:8e1d with SMTP id v30-20020a056a207d9e00b000cd8ed88e1dmr25840172pzj.12.1678442331828; Fri, 10 Mar 2023 01:58:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678442331; cv=none; d=google.com; s=arc-20160816; b=Rzr4NY66Yarz/KTm9JqwyL/xcqTKQ6YaP52F8vtfquuUVM1kH1b0IryndkxY+13tBs wV/0/MP/ETS35YpJUVrifprU1zv7+7PN6CxtddSDDvjBZwriwnaBEXBIgs/HmOcqz/hv QIo5fmKHDp6DoG5g29ZRIMH38x7QgymOGRGuTFF0EkQhQTfCtY1GnyXjjXyFyUFMD1eT 1jBxKrs6iiaaE1bl3VUZLpyKqoXBWq/Fwrdb0GNHHitrXvW5q8ZigbKYsOSZXY/d2OTA Xmva8eh2b9L3xk5Il3xPWJaQWT7pKmOf7uMzOD7BBl6dy1mIL5b07o9sB8G0oEeEoJ0u 3J1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=HA1xGrUXWy21CUhjf+7eNgybjNNpOnIGNYQsit2KPGw=; b=kOQnXC2Qd5jh5Y+K5lcKqXPlajbpmhEHrBuxCeUL/UN78rXISrQI7ju36M17fg9OC/ E/qm/MZpPx1RrwaJ4XmaXSYSbswSmjpcvUwNDGMWQgJ5JA9awHRAOND4SDV05Z5LY2mT wJLU5/Mo5ZigB8L8YkITMeik1miK9BClIeOKyugEhMP4Cf+I2IykQ4yW+uBbWATg7dvv 32+WzZkQEMGi66lYIv1dgwfS3A2nrk1i2OQIIN9lZT+6HKqDPh/v3+Bf6sIpmEcPMYKs PG4WLeYwdPrk40CEY8z1Y9jgOxnapuLMYc5xrov7eaaXBPTvreYPjgiwE9U/cG/3Idgu ciuw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20210112.gappssmtp.com header.s=20210112 header.b="REcz0/NG"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id p2-20020a631e42000000b004fc2dfedcd6si1596026pgm.213.2023.03.10.01.58.38; Fri, 10 Mar 2023 01:58:51 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20210112.gappssmtp.com header.s=20210112 header.b="REcz0/NG"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231536AbjCJJuj (ORCPT + 99 others); Fri, 10 Mar 2023 04:50:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51196 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231171AbjCJJuP (ORCPT ); Fri, 10 Mar 2023 04:50:15 -0500 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B0287E842A for ; Fri, 10 Mar 2023 01:49:49 -0800 (PST) Received: by mail-wr1-x42e.google.com with SMTP id bw19so4444614wrb.13 for ; Fri, 10 Mar 2023 01:49:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; t=1678441788; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HA1xGrUXWy21CUhjf+7eNgybjNNpOnIGNYQsit2KPGw=; b=REcz0/NGalsvL8YM5VfJHGHT+5Zx9APaiOS7xrZg8vWiQvcinmscsaMLtiXL7so4g4 41M5LnQ2wVaXuUl7sADBqjFOMycg8WFYosksCMrnpc5qWRhxzHgeLLpV/03M+KC8kySS 8lN49Sh4azp4adigJ06tqmHfix+oQUOTa7NKgV/8PfSZvFpDmmAU3T/8w3VjOJuIwRiT Xj2IHrW/U++aBXMB8awyytbIHjvJWW3jQCzeGF4aCAtzfxvlyWSTwBOGN9PFGet2iJY0 VMETw28kNRWzYTA48sQoBXr75q3gCuVRXpvBKfX5dzJbm/a/31uCTNfAl3rk4YehFWUU Jnuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678441788; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HA1xGrUXWy21CUhjf+7eNgybjNNpOnIGNYQsit2KPGw=; b=mptwfAn4qybbruB74CuFUkaOVuNDucN0GGLKaAd4EfmZbxJ9B6tfGmHyzd6NrbRmig RnC+xOL0BMSx3KFOsKR8YsUoSKJ2jjq0MdYhJqe+QEZlB2HLCGJGPPMgI3zl6kgYXc+F 5j1nOwCYCExKPhm/eUfZ/B0FtL7uqz57Z4z7B4X829fXw8X8+zreIKl8aTr3f30dzuvV R9mR8YL9JJJUvyh/bs/ihfXZFeDTXuoiAHGHJw8KqsIuVl8yPrGJ7vR7RD1EpwBZTixQ 48f260VSx+KJm5zjkcW8VbER3V23DJMT1vTNAv+P/uqs4HNosk69kTlxF9jO1qJSqFrO vgmg== X-Gm-Message-State: AO0yUKWAUNkvdVrdCbAZy8zpbKBcvtLpkfsC7KDYRP1WKaBIEO1+vYjy uaHiRScv3njHUiqpDcrFclmx7g== X-Received: by 2002:adf:dd87:0:b0:2c5:4c5e:412b with SMTP id x7-20020adfdd87000000b002c54c5e412bmr852346wrl.23.1678441788090; Fri, 10 Mar 2023 01:49:48 -0800 (PST) Received: from alex-rivos.ba.rivosinc.com (amontpellier-656-1-456-62.w92-145.abo.wanadoo.fr. [92.145.124.62]) by smtp.gmail.com with ESMTPSA id n22-20020a7bc5d6000000b003eaf666cbe0sm1616174wmk.27.2023.03.10.01.49.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Mar 2023 01:49:47 -0800 (PST) From: Alexandre Ghiti To: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , Rob Herring , Frank Rowand , Mike Rapoport , Andrew Morton , Anup Patel , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-mm@kvack.org Cc: Alexandre Ghiti , Rob Herring , Andrew Jones Subject: [PATCH v7 4/4] riscv: Use PUD/P4D/PGD pages for the linear mapping Date: Fri, 10 Mar 2023 10:45:39 +0100 Message-Id: <20230310094539.764357-5-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230310094539.764357-1-alexghiti@rivosinc.com> References: <20230310094539.764357-1-alexghiti@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759974346784561954?= X-GMAIL-MSGID: =?utf-8?q?1759974346784561954?= During the early page table creation, we used to set the mapping for PAGE_OFFSET to the kernel load address: but the kernel load address is always offseted by PMD_SIZE which makes it impossible to use PUD/P4D/PGD pages as this physical address is not aligned on PUD/P4D/PGD size (whereas PAGE_OFFSET is). But actually we don't have to establish this mapping (ie set va_pa_offset) that early in the boot process because: - first, setup_vm installs a temporary kernel mapping and among other things, discovers the system memory, - then, setup_vm_final creates the final kernel mapping and takes advantage of the discovered system memory to create the linear mapping. During the first phase, we don't know the start of the system memory and then until the second phase is finished, we can't use the linear mapping at all and phys_to_virt/virt_to_phys translations must not be used because it would result in a different translation from the 'real' one once the final mapping is installed. So here we simply delay the initialization of va_pa_offset to after the system memory discovery. But to make sure noone uses the linear mapping before, we add some guard in the DEBUG_VIRTUAL config. Finally we can use PUD/P4D/PGD hugepages when possible, which will result in a better TLB utilization. Note that we rely on the firmware to protect itself using PMP. Signed-off-by: Alexandre Ghiti Acked-by: Rob Herring # DT bits Reviewed-by: Andrew Jones --- arch/riscv/include/asm/page.h | 16 ++++++++++++++++ arch/riscv/mm/init.c | 35 +++++++++++++++++++++++++++++------ arch/riscv/mm/physaddr.c | 16 ++++++++++++++++ drivers/of/fdt.c | 11 ++++++----- 4 files changed, 67 insertions(+), 11 deletions(-) diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h index 8dc686f549b6..ea1a0e237211 100644 --- a/arch/riscv/include/asm/page.h +++ b/arch/riscv/include/asm/page.h @@ -90,6 +90,14 @@ typedef struct page *pgtable_t; #define PTE_FMT "%08lx" #endif +#ifdef CONFIG_64BIT +/* + * We override this value as its generic definition uses __pa too early in + * the boot process (before kernel_map.va_pa_offset is set). + */ +#define MIN_MEMBLOCK_ADDR 0 +#endif + #ifdef CONFIG_MMU #define ARCH_PFN_OFFSET (PFN_DOWN((unsigned long)phys_ram_base)) #else @@ -121,7 +129,11 @@ extern phys_addr_t phys_ram_base; #define is_linear_mapping(x) \ ((x) >= PAGE_OFFSET && (!IS_ENABLED(CONFIG_64BIT) || (x) < PAGE_OFFSET + KERN_VIRT_SIZE)) +#ifndef CONFIG_DEBUG_VIRTUAL #define linear_mapping_pa_to_va(x) ((void *)((unsigned long)(x) + kernel_map.va_pa_offset)) +#else +void *linear_mapping_pa_to_va(unsigned long x); +#endif #define kernel_mapping_pa_to_va(y) ({ \ unsigned long _y = (unsigned long)(y); \ (IS_ENABLED(CONFIG_XIP_KERNEL) && _y < phys_ram_base) ? \ @@ -130,7 +142,11 @@ extern phys_addr_t phys_ram_base; }) #define __pa_to_va_nodebug(x) linear_mapping_pa_to_va(x) +#ifndef CONFIG_DEBUG_VIRTUAL #define linear_mapping_va_to_pa(x) ((unsigned long)(x) - kernel_map.va_pa_offset) +#else +phys_addr_t linear_mapping_va_to_pa(unsigned long x); +#endif #define kernel_mapping_va_to_pa(y) ({ \ unsigned long _y = (unsigned long)(y); \ (IS_ENABLED(CONFIG_XIP_KERNEL) && _y < kernel_map.virt_addr + XIP_OFFSET) ? \ diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index 225a7d2b65cc..fed5109d27db 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -213,6 +213,13 @@ static void __init setup_bootmem(void) phys_ram_end = memblock_end_of_DRAM(); if (!IS_ENABLED(CONFIG_XIP_KERNEL)) phys_ram_base = memblock_start_of_DRAM(); + + /* + * Any use of __va/__pa before this point is wrong as we did not know the + * start of DRAM before. + */ + kernel_map.va_pa_offset = PAGE_OFFSET - phys_ram_base; + /* * memblock allocator is not aware of the fact that last 4K bytes of * the addressable memory can not be mapped because of IS_ERR_VALUE @@ -667,9 +674,16 @@ void __init create_pgd_mapping(pgd_t *pgdp, static uintptr_t __init best_map_size(phys_addr_t base, phys_addr_t size) { - /* Upgrade to PMD_SIZE mappings whenever possible */ - base &= PMD_SIZE - 1; - if (!base && size >= PMD_SIZE) + if (!(base & (PGDIR_SIZE - 1)) && size >= PGDIR_SIZE) + return PGDIR_SIZE; + + if (!(base & (P4D_SIZE - 1)) && size >= P4D_SIZE) + return P4D_SIZE; + + if (!(base & (PUD_SIZE - 1)) && size >= PUD_SIZE) + return PUD_SIZE; + + if (!(base & (PMD_SIZE - 1)) && size >= PMD_SIZE) return PMD_SIZE; return PAGE_SIZE; @@ -978,11 +992,9 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa) set_satp_mode(); #endif - kernel_map.va_pa_offset = PAGE_OFFSET - kernel_map.phys_addr; + kernel_map.va_pa_offset = 0UL; kernel_map.va_kernel_pa_offset = kernel_map.virt_addr - kernel_map.phys_addr; - phys_ram_base = kernel_map.phys_addr; - /* * The default maximal physical memory size is KERN_VIRT_SIZE for 32-bit * kernel, whereas for 64-bit kernel, the end of the virtual address @@ -1097,6 +1109,17 @@ static void __init setup_vm_final(void) __pa_symbol(fixmap_pgd_next), PGDIR_SIZE, PAGE_TABLE); +#ifdef CONFIG_STRICT_KERNEL_RWX + /* + * Isolate the kernel text and rodata linear so they don't + * get mapped with a PUD in the linear mapping. + */ + memblock_isolate_memory(__pa_symbol(_start), + __init_data_begin - _start); + memblock_isolate_memory(__pa_symbol(__start_rodata), + __start_rodata - _data); +#endif + /* Map all memory banks in the linear mapping */ for_each_mem_range(i, &start, &end) { if (start >= end) diff --git a/arch/riscv/mm/physaddr.c b/arch/riscv/mm/physaddr.c index 9b18bda74154..18706f457da7 100644 --- a/arch/riscv/mm/physaddr.c +++ b/arch/riscv/mm/physaddr.c @@ -33,3 +33,19 @@ phys_addr_t __phys_addr_symbol(unsigned long x) return __va_to_pa_nodebug(x); } EXPORT_SYMBOL(__phys_addr_symbol); + +phys_addr_t linear_mapping_va_to_pa(unsigned long x) +{ + BUG_ON(!kernel_map.va_pa_offset); + + return ((unsigned long)(x) - kernel_map.va_pa_offset); +} +EXPORT_SYMBOL(linear_mapping_va_to_pa); + +void *linear_mapping_pa_to_va(unsigned long x) +{ + BUG_ON(!kernel_map.va_pa_offset); + + return ((void *)((unsigned long)(x) + kernel_map.va_pa_offset)); +} +EXPORT_SYMBOL(linear_mapping_pa_to_va); diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c index d1a68b6d03b3..d14735a81301 100644 --- a/drivers/of/fdt.c +++ b/drivers/of/fdt.c @@ -887,12 +887,13 @@ const void * __init of_flat_dt_match_machine(const void *default_match, static void __early_init_dt_declare_initrd(unsigned long start, unsigned long end) { - /* ARM64 would cause a BUG to occur here when CONFIG_DEBUG_VM is - * enabled since __va() is called too early. ARM64 does make use - * of phys_initrd_start/phys_initrd_size so we can skip this - * conversion. + /* + * __va() is not yet available this early on some platforms. In that + * case, the platform uses phys_initrd_start/phys_initrd_size instead + * and does the VA conversion itself. */ - if (!IS_ENABLED(CONFIG_ARM64)) { + if (!IS_ENABLED(CONFIG_ARM64) && + !(IS_ENABLED(CONFIG_RISCV) && IS_ENABLED(CONFIG_64BIT))) { initrd_start = (unsigned long)__va(start); initrd_end = (unsigned long)__va(end); initrd_below_start_ok = 1;