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[2620:137:e000::1:20]) by mx.google.com with ESMTP id c19-20020a170902c1d300b0019ad7bad651si1082622plc.4.2023.03.09.20.28.27; Thu, 09 Mar 2023 20:28:39 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FLaiNGtf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230378AbjCJEKc (ORCPT + 99 others); Thu, 9 Mar 2023 23:10:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33704 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230296AbjCJEJd (ORCPT ); Thu, 9 Mar 2023 23:09:33 -0500 Received: from mail-pg1-x529.google.com (mail-pg1-x529.google.com [IPv6:2607:f8b0:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D6EFD13E3 for ; Thu, 9 Mar 2023 20:09:13 -0800 (PST) Received: by mail-pg1-x529.google.com with SMTP id q23so2354082pgt.7 for ; Thu, 09 Mar 2023 20:09:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678421350; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HLaHkNbeR3pTSpm3EckvQkVoLPurUbKikH/yYKtcjD0=; b=FLaiNGtfenzg4g6Mbm7oxjaBUpioBOFkqZ/JmfPiiqIxihchNyEXTg+/ALMzvZiOMa AIUeAJr8uz3ikL5e0P0wxSqJWoHnXinYUGye8mhttjbihQ42Q32AnOaAUXa46+PP0G0X SfRWz/X4f5HTUUMTnE6APpg7aDQ8W8SUtC/oHjG03AQC7XzNNt0V2/1h9ePUL3rp6PdG XN84d1vPslDI9lPdzAc7w9MXdqT5JGxBL8rdXCV7+6L8WUp9pAcfQCd+NaxGkRhUKpE+ rAZV81CChcrvlC4ea3AjeBBuND/ueAc2YIAKoGtUmBoGFVlEeKgTHDmMDYFyopFOkk2P euXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678421350; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HLaHkNbeR3pTSpm3EckvQkVoLPurUbKikH/yYKtcjD0=; b=J7Xb/9V7gFBVQ6kKXbUejmBYhC+S0qGjhU2Z1wjv4L77VzAz826R23q77vDEhp7YM2 S4y3fMVy1l655mVxegB8QhodkoyyhsegD0EsesHOi5cQ2s4RJ7llPHeCIxLVeU5QleDs DEEIn3h51mr73lZLPylqsdliowoAEWFodeiZadvprHQm19GHAWGIRwaAwuElhz9KVCl6 S5/VDh426mk2FhDEIDFIHIaKuI/1jwygOY5SA90NF4LHnyeFyCvbWKf24cVCQAG3pakL n2MI5UcBb517/xyIV2j/a/njXyTJrZXCZwGwTjDeYpA6TqrU/cETF+UKTDiJdjyv4Tmd Kf2g== X-Gm-Message-State: AO0yUKUX+rwBY8mpjENHXWjwraP8Mm1judLi/QgN+dF1YZW7GshnwI3G bU1KnVZ9/Io+24tHdpMiSzUt X-Received: by 2002:a62:1a43:0:b0:5a8:ecb1:bf1 with SMTP id a64-20020a621a43000000b005a8ecb10bf1mr17304947pfa.19.1678421350259; Thu, 09 Mar 2023 20:09:10 -0800 (PST) Received: from localhost.localdomain ([27.111.75.67]) by smtp.gmail.com with ESMTPSA id y26-20020aa7855a000000b0058d92d6e4ddsm361846pfn.5.2023.03.09.20.09.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 20:09:09 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v3 09/19] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.3 Date: Fri, 10 Mar 2023 09:38:06 +0530 Message-Id: <20230310040816.22094-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> References: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759953571929008676?= X-GMAIL-MSGID: =?utf-8?q?1759953571929008676?= All the clocks are enabled and disabled at the same time. So the bulk clock APIs can be used to handle them together. This simplifies the code a lot. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 88 ++++++-------------------- 1 file changed, 20 insertions(+), 68 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 939973733a1e..6b83e3627336 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -169,6 +169,12 @@ struct qcom_pcie_resources_2_3_2 { struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY]; }; +#define QCOM_PCIE_2_3_3_MAX_CLOCKS 5 +struct qcom_pcie_resources_2_3_3 { + struct clk_bulk_data clks[QCOM_PCIE_2_3_3_MAX_CLOCKS]; + struct reset_control *rst[7]; +}; + #define QCOM_PCIE_2_4_0_MAX_CLOCKS 4 struct qcom_pcie_resources_2_4_0 { struct clk_bulk_data clks[QCOM_PCIE_2_4_0_MAX_CLOCKS]; @@ -187,15 +193,6 @@ struct qcom_pcie_resources_2_4_0 { struct reset_control *phy_ahb_reset; }; -struct qcom_pcie_resources_2_3_3 { - struct clk *iface; - struct clk *axi_m_clk; - struct clk *axi_s_clk; - struct clk *ahb_clk; - struct clk *aux_clk; - struct reset_control *rst[7]; -}; - /* 6 clocks typically, 7 for sm8250 */ struct qcom_pcie_resources_2_7_0 { struct clk_bulk_data clks[12]; @@ -896,26 +893,17 @@ static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie) const char *rst_names[] = { "axi_m", "axi_s", "pipe", "axi_m_sticky", "sticky", "ahb", "sleep", }; + int ret; - res->iface = devm_clk_get(dev, "iface"); - if (IS_ERR(res->iface)) - return PTR_ERR(res->iface); - - res->axi_m_clk = devm_clk_get(dev, "axi_m"); - if (IS_ERR(res->axi_m_clk)) - return PTR_ERR(res->axi_m_clk); - - res->axi_s_clk = devm_clk_get(dev, "axi_s"); - if (IS_ERR(res->axi_s_clk)) - return PTR_ERR(res->axi_s_clk); - - res->ahb_clk = devm_clk_get(dev, "ahb"); - if (IS_ERR(res->ahb_clk)) - return PTR_ERR(res->ahb_clk); + res->clks[0].id = "iface"; + res->clks[1].id = "axi_m"; + res->clks[2].id = "axi_s"; + res->clks[3].id = "ahb"; + res->clks[4].id = "aux"; - res->aux_clk = devm_clk_get(dev, "aux"); - if (IS_ERR(res->aux_clk)) - return PTR_ERR(res->aux_clk); + ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); + if (ret < 0) + return ret; for (i = 0; i < ARRAY_SIZE(rst_names); i++) { res->rst[i] = devm_reset_control_get(dev, rst_names[i]); @@ -930,11 +918,7 @@ static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; - clk_disable_unprepare(res->iface); - clk_disable_unprepare(res->axi_m_clk); - clk_disable_unprepare(res->axi_s_clk); - clk_disable_unprepare(res->ahb_clk); - clk_disable_unprepare(res->aux_clk); + clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); } static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) @@ -969,47 +953,15 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) */ usleep_range(2000, 2500); - ret = clk_prepare_enable(res->iface); - if (ret) { - dev_err(dev, "cannot prepare/enable core clock\n"); - goto err_clk_iface; - } - - ret = clk_prepare_enable(res->axi_m_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable core clock\n"); - goto err_clk_axi_m; - } - - ret = clk_prepare_enable(res->axi_s_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable axi slave clock\n"); - goto err_clk_axi_s; - } - - ret = clk_prepare_enable(res->ahb_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable ahb clock\n"); - goto err_clk_ahb; - } - - ret = clk_prepare_enable(res->aux_clk); + ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); if (ret) { - dev_err(dev, "cannot prepare/enable aux clock\n"); - goto err_clk_aux; + dev_err(dev, "cannot prepare/enable clocks\n"); + goto err_assert_resets; } return 0; -err_clk_aux: - clk_disable_unprepare(res->ahb_clk); -err_clk_ahb: - clk_disable_unprepare(res->axi_s_clk); -err_clk_axi_s: - clk_disable_unprepare(res->axi_m_clk); -err_clk_axi_m: - clk_disable_unprepare(res->iface); -err_clk_iface: +err_assert_resets: /* * Not checking for failure, will anyway return * the original failure in 'ret'.