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[2620:137:e000::1:20]) by mx.google.com with ESMTP id f133-20020a1f9c8b000000b0040f34a80024si501081vke.211.2023.03.09.20.02.36; Thu, 09 Mar 2023 20:02:51 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linux.dev header.s=key1 header.b=soK4Htsl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linux.dev Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229994AbjCJDYE (ORCPT + 99 others); Thu, 9 Mar 2023 22:24:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54726 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230009AbjCJDYB (ORCPT ); Thu, 9 Mar 2023 22:24:01 -0500 Received: from out-39.mta0.migadu.com (out-39.mta0.migadu.com [IPv6:2001:41d0:1004:224b::27]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E2BB880E2A for ; Thu, 9 Mar 2023 19:23:59 -0800 (PST) X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1678418637; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=cSKnAfT4v272o6UVisajOb3ZSGXKqhYt674hgTSKgpU=; b=soK4HtslPOIamcOls0IMI+e/jcXCc6XD1t0/rYnGncrNbJ2ojsXswe7U2XFNonXtfpd47c O9zRm+bzyLuSwfg24vNGAzOC8E12zHRuBUPMVqLAK05QyvnrFmAc7lt7JIR3hYC4cMXneJ Fh6A3xdTL5TukVf98i0nV22NW1yWU2s= From: Cai Huoqing To: fancer.lancer@gmail.com Cc: Cai huoqing , Gustavo Pimentel , Vinod Koul , Jingoo Han , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v6 1/5] dmaengine: dw-edma: Rename dw_edma_core_ops structure to dw_edma_plat_ops Date: Fri, 10 Mar 2023 11:23:34 +0800 Message-Id: <20230310032342.17395-2-cai.huoqing@linux.dev> In-Reply-To: <20230310032342.17395-1-cai.huoqing@linux.dev> References: <20230310032342.17395-1-cai.huoqing@linux.dev> MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759951948813055868?= X-GMAIL-MSGID: =?utf-8?q?1759951948813055868?= From: Cai huoqing Rename dw_edma_core_ops structure to dw_edma_plat_ops, the ops is platform specific operations: the DMA device environment configs like IRQs, address translation, etc. The dw_edma_core_ops structure contains a set of the operations: device IRQ numbers getter, CPU/PCI address translation. Based on the functions semantics the structure name "dw_edma_plat_ops" looks more descriptive since indeed the operations are platform-specific. The "dw_edma_core_ops" name shall be used for a structure with the IP-core specific set of callbacks in order to abstract out DW eDMA and DW HDMA setups. Such structure will be added in one of the next commit in the framework of the set of changes adding the DW HDMA device support. Anyway the renaming was necessary to distinguish two types of the implementation callbacks: 1. DW eDMA/hDMA IP-core specific operations: device-specific CSR setups in one or another aspect of the DMA-engine initialization. 2. DW eDMA/hDMA platform specific operations: the DMA device environment configs like IRQs, address translation, etc. dw_edma_core_ops is supposed to be used for the case 1, and dw_edma_plat_ops - for the case 2. Signed-off-by: Cai huoqing Reviewed-by: Serge Semin --- v5->v6: 1.Change the commit log to explain dw_edma_core_ops structure. 2.Revert the instance dw_edma_pcie_plat_ops. v5 link: https://lore.kernel.org/lkml/20230303124642.5519-2-cai.huoqing@linux.dev/ drivers/dma/dw-edma/dw-edma-pcie.c | 4 ++-- drivers/pci/controller/dwc/pcie-designware.c | 2 +- include/linux/dma/edma.h | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c index 2b40f2b44f5e..1c6043751dc9 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -109,7 +109,7 @@ static u64 dw_edma_pcie_address(struct device *dev, phys_addr_t cpu_addr) return region.start; } -static const struct dw_edma_core_ops dw_edma_pcie_core_ops = { +static const struct dw_edma_plat_ops dw_edma_pcie_plat_ops = { .irq_vector = dw_edma_pcie_irq_vector, .pci_address = dw_edma_pcie_address, }; @@ -225,7 +225,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, chip->mf = vsec_data.mf; chip->nr_irqs = nr_irqs; - chip->ops = &dw_edma_pcie_core_ops; + chip->ops = &dw_edma_pcie_plat_ops; chip->ll_wr_cnt = vsec_data.wr_ch_cnt; chip->ll_rd_cnt = vsec_data.rd_ch_cnt; diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 53a16b8b6ac2..44e90b71d429 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -828,7 +828,7 @@ static int dw_pcie_edma_irq_vector(struct device *dev, unsigned int nr) return platform_get_irq_byname_optional(pdev, name); } -static struct dw_edma_core_ops dw_pcie_edma_ops = { +static struct dw_edma_plat_ops dw_pcie_edma_ops = { .irq_vector = dw_pcie_edma_irq_vector, }; diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h index d2638d9259dc..ed401c965a87 100644 --- a/include/linux/dma/edma.h +++ b/include/linux/dma/edma.h @@ -40,7 +40,7 @@ struct dw_edma_region { * iATU windows. That will be done by the controller * automatically. */ -struct dw_edma_core_ops { +struct dw_edma_plat_ops { int (*irq_vector)(struct device *dev, unsigned int nr); u64 (*pci_address)(struct device *dev, phys_addr_t cpu_addr); }; @@ -80,7 +80,7 @@ enum dw_edma_chip_flags { struct dw_edma_chip { struct device *dev; int nr_irqs; - const struct dw_edma_core_ops *ops; + const struct dw_edma_plat_ops *ops; u32 flags; void __iomem *reg_base;