diff mbox series

[v2,4/5] iommu/vt-d: Move pfsid and ats_qdep calculation to device probe path

Message ID 20230309025639.26109-5-baolu.lu@linux.intel.com
State New
Headers
Series Refactor code for non-PRI IOPF |

Commit Message

Baolu Lu March 9, 2023, 2:56 a.m. UTC 
  They should be part of the per-device iommu private data initialization.

Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
---
 drivers/iommu/intel/iommu.c | 26 +++++++++++---------------
 1 file changed, 11 insertions(+), 15 deletions(-)

Comments

Tian, Kevin March 16, 2023, 7:10 a.m. UTC | #1 
> From: Lu Baolu <baolu.lu@linux.intel.com>
> Sent: Thursday, March 9, 2023 10:57 AM
> 
> They should be part of the per-device iommu private data initialization.
> 
> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>

Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Jacob Pan March 20, 2023, 4:11 p.m. UTC | #2 
Hi BaoLu,

On Thu,  9 Mar 2023 10:56:38 +0800, Lu Baolu <baolu.lu@linux.intel.com>
wrote:

> They should be part of the per-device iommu private data initialization.
> 
Reviewed-by: Jacob Pan <jacob.jun.pan@linux.intel.com>

> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
> ---
>  drivers/iommu/intel/iommu.c | 26 +++++++++++---------------
>  1 file changed, 11 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
> index 9ada12bf38dd..fb64ab8358a9 100644
> --- a/drivers/iommu/intel/iommu.c
> +++ b/drivers/iommu/intel/iommu.c
> @@ -1406,20 +1406,6 @@ static void iommu_enable_pci_caps(struct
> device_domain_info *info) return;
>  
>  	pdev = to_pci_dev(info->dev);
> -	/* For IOMMU that supports device IOTLB throttling (DIT), we
> assign
> -	 * PFSID to the invalidation desc of a VF such that IOMMU HW can
> gauge
> -	 * queue depth at PF level. If DIT is not set, PFSID will be
> treated as
> -	 * reserved, which should be set to 0.
> -	 */
> -	if (!ecap_dit(info->iommu->ecap))
> -		info->pfsid = 0;
> -	else {
> -		struct pci_dev *pf_pdev;
> -
> -		/* pdev will be returned if device is not a vf */
> -		pf_pdev = pci_physfn(pdev);
> -		info->pfsid = pci_dev_id(pf_pdev);
> -	}
>  
>  	/* The PCIe spec, in its wisdom, declares that the behaviour of
>  	   the device if you enable PASID support after ATS support is
> @@ -1438,7 +1424,6 @@ static void iommu_enable_pci_caps(struct
> device_domain_info *info) !pci_enable_ats(pdev, VTD_PAGE_SHIFT)) {
>  		info->ats_enabled = 1;
>  		domain_update_iotlb(info->domain);
> -		info->ats_qdep = pci_ats_queue_depth(pdev);
>  	}
>  }
>  
> @@ -4521,6 +4506,17 @@ static struct iommu_device
> *intel_iommu_probe_device(struct device *dev) dmar_ats_supported(pdev,
> iommu)) { info->ats_supported = 1;
>  			info->dtlb_extra_inval =
> dev_needs_extra_dtlb_flush(pdev); +
> +			/*
> +			 * For IOMMU that supports device IOTLB
> throttling
> +			 * (DIT), we assign PFSID to the invalidation
> desc
> +			 * of a VF such that IOMMU HW can gauge queue
> depth
> +			 * at PF level. If DIT is not set, PFSID will be
> +			 * treated as reserved, which should be set to 0.
> +			 */
> +			if (ecap_dit(iommu->ecap))
> +				info->pfsid =
> pci_dev_id(pci_physfn(pdev));
> +			info->ats_qdep = pci_ats_queue_depth(pdev);
>  		}
>  		if (sm_supported(iommu)) {
>  			if (pasid_supported(iommu)) {


Thanks,

Jacob
diff mbox series

Patch

diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index 9ada12bf38dd..fb64ab8358a9 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -1406,20 +1406,6 @@  static void iommu_enable_pci_caps(struct device_domain_info *info)
 		return;
 
 	pdev = to_pci_dev(info->dev);
-	/* For IOMMU that supports device IOTLB throttling (DIT), we assign
-	 * PFSID to the invalidation desc of a VF such that IOMMU HW can gauge
-	 * queue depth at PF level. If DIT is not set, PFSID will be treated as
-	 * reserved, which should be set to 0.
-	 */
-	if (!ecap_dit(info->iommu->ecap))
-		info->pfsid = 0;
-	else {
-		struct pci_dev *pf_pdev;
-
-		/* pdev will be returned if device is not a vf */
-		pf_pdev = pci_physfn(pdev);
-		info->pfsid = pci_dev_id(pf_pdev);
-	}
 
 	/* The PCIe spec, in its wisdom, declares that the behaviour of
 	   the device if you enable PASID support after ATS support is
@@ -1438,7 +1424,6 @@  static void iommu_enable_pci_caps(struct device_domain_info *info)
 	    !pci_enable_ats(pdev, VTD_PAGE_SHIFT)) {
 		info->ats_enabled = 1;
 		domain_update_iotlb(info->domain);
-		info->ats_qdep = pci_ats_queue_depth(pdev);
 	}
 }
 
@@ -4521,6 +4506,17 @@  static struct iommu_device *intel_iommu_probe_device(struct device *dev)
 		    dmar_ats_supported(pdev, iommu)) {
 			info->ats_supported = 1;
 			info->dtlb_extra_inval = dev_needs_extra_dtlb_flush(pdev);
+
+			/*
+			 * For IOMMU that supports device IOTLB throttling
+			 * (DIT), we assign PFSID to the invalidation desc
+			 * of a VF such that IOMMU HW can gauge queue depth
+			 * at PF level. If DIT is not set, PFSID will be
+			 * treated as reserved, which should be set to 0.
+			 */
+			if (ecap_dit(iommu->ecap))
+				info->pfsid = pci_dev_id(pci_physfn(pdev));
+			info->ats_qdep = pci_ats_queue_depth(pdev);
 		}
 		if (sm_supported(iommu)) {
 			if (pasid_supported(iommu)) {