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[2620:137:e000::1:20]) by mx.google.com with ESMTP id l3-20020a056402124300b004c0e614f887si15833494edw.94.2023.03.08.00.44.20; Wed, 08 Mar 2023 00:44:44 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pYrW1o8q; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229991AbjCHIZ7 (ORCPT + 99 others); Wed, 8 Mar 2023 03:25:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229717AbjCHIZG (ORCPT ); Wed, 8 Mar 2023 03:25:06 -0500 Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B00DE43479 for ; Wed, 8 Mar 2023 00:25:03 -0800 (PST) Received: by mail-pj1-x1033.google.com with SMTP id h17-20020a17090aea9100b0023739b10792so1205979pjz.1 for ; Wed, 08 Mar 2023 00:25:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678263903; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FkX/JAqnQ5TtZN/6y4NG0baYlpvwEsEM/sqYpvaAueY=; b=pYrW1o8qgI7rZ64QiXnQOKoVsn/OKOvGyNVVqyntAXjDVb8lA0bB7eR8VotlSINd83 M7I6HL8Z4zp8bbu2Y7ZHYD4YfPfIu1pdRby0kMBhT+27rOyADci1fAZP/vaMwuF7RsPV 3Qp3r/lWJWSZhb6ngMGgdbfaa8WvWawTzxkbBsKmlaeavGmvmgqgixgILaL0g3R6cPgF p81yICU7FggoQ+hHRAADGKpuCxLCWiaqZGETaZc4YrkUngakBeKHtSlHfKoifQru1ZpD cox+SciUU7Kn9I6Nv+W0o/HQTukFRC6QnU3FBhCk29XPkrunPL9YVMAwbnOC7u86UJQl DR7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678263903; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FkX/JAqnQ5TtZN/6y4NG0baYlpvwEsEM/sqYpvaAueY=; b=yclGp/G2MLUy+9D/uWfhTsXBr71FADBSUxYuFmJUAfobjkR69v93M7Ycx/7K1srgx1 5NOtxpVOUSK4QH1wRC1rLFTX8KBa20Vmwn8W+6lwd5qiPj2t8thlzSkf+XX5+xWSVGcl OpurHPRghKVyaJFSTwqjcFgurZA1FMQy0wmOblmlp3jngI8H18ndZGPqVswEPsIbm2Mj 1T1wUni6VcbaQ7bHOSVHLMFpmYNAum0qx3DEoWqVU8y9ZY18JPGBMPmrWPwybh/Jv/QF i7kgG2sHuVm1FxgkptRaVb9Dhg8EXZ5iZkbTU4b4JGW8r+qDkpQrlEW17pPBt5Z3/32i IBnA== X-Gm-Message-State: AO0yUKWGvD1LUAIzi8yw1I47J82SVmcBbT9HRfmmo9i8SxIpygT1QLaG l/XCc9TYbW78JF5LmCWXneRs X-Received: by 2002:a17:903:11cf:b0:19e:6b50:e220 with SMTP id q15-20020a17090311cf00b0019e6b50e220mr7487131plh.53.1678263903123; Wed, 08 Mar 2023 00:25:03 -0800 (PST) Received: from localhost.localdomain ([59.97.52.140]) by smtp.gmail.com with ESMTPSA id s10-20020a170902ea0a00b0019aaab3f9d7sm9448086plg.113.2023.03.08.00.24.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 00:25:02 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v3 07/13] ARM: dts: qcom: sdx55: Add support for PCIe RC controller Date: Wed, 8 Mar 2023 13:54:18 +0530 Message-Id: <20230308082424.140224-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230308082424.140224-1-manivannan.sadhasivam@linaro.org> References: <20230308082424.140224-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759788488888480090?= X-GMAIL-MSGID: =?utf-8?q?1759788488888480090?= The PCIe controller in SDX55 can act as the RC controller also. Let's add support for it. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55.dtsi | 81 +++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index bd4edceaa1f4..9dabb94eafbc 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -304,6 +304,87 @@ qpic_nand: nand-controller@1b30000 { status = "disabled"; }; + pcie_rc: pcie@1c00000 { + compatible = "qcom,pcie-sdx55"; + reg = <0x01c00000 0x3000>, + <0x40000000 0xf1d>, + <0x40000f20 0xc8>, + <0x40001000 0x1000>, + <0x40100000 0x100000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x00000000 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "msi8"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 141 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 144 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_PIPE_CLK>, + <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "sleep"; + + assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>; + assigned-clock-rates = <19200000>; + + iommu-map = <0x0 &apps_smmu 0x0200 0x1>, + <0x100 &apps_smmu 0x0201 0x1>, + <0x200 &apps_smmu 0x0202 0x1>, + <0x300 &apps_smmu 0x0203 0x1>, + <0x400 &apps_smmu 0x0204 0x1>; + + resets = <&gcc GCC_PCIE_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_GDSC>; + + phys = <&pcie_lane>; + phy-names = "pciephy"; + + status = "disabled"; + }; + pcie_ep: pcie-ep@1c00000 { compatible = "qcom,sdx55-pcie-ep"; reg = <0x01c00000 0x3000>,