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From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: andersson@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org
Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Subject: [PATCH] arm64: dts: qcom: sm8550: Mark UFS controller as cache
coherent
Date: Wed, 8 Mar 2023 11:16:30 +0530
Message-Id: <20230308054630.7202-1-manivannan.sadhasivam@linaro.org>
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arm64: dts: qcom: sm8550: Mark UFS controller as cache coherent
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Commit Message
Manivannan Sadhasivam
March 8, 2023, 5:46 a.m. UTC
The UFS controller on SM8550 supports cache coherency, hence add the
"dma-coherent" property to mark it as such.
Fixes: 35cf1aaab169 ("arm64: dts: qcom: sm8550: Add UFS host controller and phy nodes")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 +
1 file changed, 1 insertion(+)
Comments
On 8.03.2023 06:46, Manivannan Sadhasivam wrote: > The UFS controller on SM8550 supports cache coherency, hence add the > "dma-coherent" property to mark it as such. > > Fixes: 35cf1aaab169 ("arm64: dts: qcom: sm8550: Add UFS host controller and phy nodes") > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- Cc: stable@vger.kernel.org # 6.2 Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi > index ff4d342c0725..5315e24fa525 100644 > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi > @@ -1905,6 +1905,7 @@ ufs_mem_hc: ufs@1d84000 { > required-opps = <&rpmhpd_opp_nom>; > > iommus = <&apps_smmu 0x60 0x0>; > + dma-coherent; > > interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, > <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
On 08/03/2023 06:46, Manivannan Sadhasivam wrote: > The UFS controller on SM8550 supports cache coherency, hence add the > "dma-coherent" property to mark it as such. > > Fixes: 35cf1aaab169 ("arm64: dts: qcom: sm8550: Add UFS host controller and phy nodes") > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi > index ff4d342c0725..5315e24fa525 100644 > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi > @@ -1905,6 +1905,7 @@ ufs_mem_hc: ufs@1d84000 { > required-opps = <&rpmhpd_opp_nom>; > > iommus = <&apps_smmu 0x60 0x0>; > + dma-coherent; > > interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, > <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
On Wed, 8 Mar 2023 11:16:30 +0530, Manivannan Sadhasivam wrote: > The UFS controller on SM8550 supports cache coherency, hence add the > "dma-coherent" property to mark it as such. > > Applied, thanks! [1/1] arm64: dts: qcom: sm8550: Mark UFS controller as cache coherent commit: ee1d5100c37e7a95af506c7addf018f652545ce6 Best regards,
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index ff4d342c0725..5315e24fa525 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1905,6 +1905,7 @@ ufs_mem_hc: ufs@1d84000 { required-opps = <&rpmhpd_opp_nom>; iommus = <&apps_smmu 0x60 0x0>; + dma-coherent; interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;