diff mbox series

perf/x86/intel: use hexidecimal value for cpuid

Message ID 20230308031501.4688-1-zhenyuw@linux.intel.com
State New
Headers
Series perf/x86/intel: use hexidecimal value for cpuid |

Commit Message

Zhenyu Wang March 8, 2023, 3:15 a.m. UTC 
  It's easier to use hexidecimal value instead of decimal for reading
and following with SDM doc, also align with other cpuid calls.

Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
---
 arch/x86/events/intel/core.c | 2 +-
 arch/x86/events/intel/lbr.c  | 2 +-
 arch/x86/events/intel/pt.c   | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

Comments

Peter Zijlstra March 8, 2023, 2:16 p.m. UTC | #1 
On Wed, Mar 08, 2023 at 11:15:01AM +0800, Zhenyu Wang wrote:
> It's easier to use hexidecimal value instead of decimal for reading
> and following with SDM doc, also align with other cpuid calls.

*shrug*..

> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
> ---
>  arch/x86/events/intel/core.c | 2 +-
>  arch/x86/events/intel/lbr.c  | 2 +-
>  arch/x86/events/intel/pt.c   | 2 +-
>  3 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index 14f0a746257d..5af084198c8f 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -5903,7 +5903,7 @@ __init int intel_pmu_init(void)
>  	 * Check whether the Architectural PerfMon supports
>  	 * Branch Misses Retired hw_event or not.
>  	 */
> -	cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full);
> +	cpuid(0xA, &eax.full, &ebx.full, &fixed_mask, &edx.full);
>  	if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
>  		return -ENODEV;

But now the data type names and the cpuid calls are no longer related.
Zhenyu Wang March 9, 2023, 1:48 a.m. UTC | #2 
On 2023.03.08 15:16:19 +0100, Peter Zijlstra wrote:
> On Wed, Mar 08, 2023 at 11:15:01AM +0800, Zhenyu Wang wrote:
> > It's easier to use hexidecimal value instead of decimal for reading
> > and following with SDM doc, also align with other cpuid calls.
> 
> *shrug*..
> 
> > Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
> > ---
> >  arch/x86/events/intel/core.c | 2 +-
> >  arch/x86/events/intel/lbr.c  | 2 +-
> >  arch/x86/events/intel/pt.c   | 2 +-
> >  3 files changed, 3 insertions(+), 3 deletions(-)
> > 
> > diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> > index 14f0a746257d..5af084198c8f 100644
> > --- a/arch/x86/events/intel/core.c
> > +++ b/arch/x86/events/intel/core.c
> > @@ -5903,7 +5903,7 @@ __init int intel_pmu_init(void)
> >  	 * Check whether the Architectural PerfMon supports
> >  	 * Branch Misses Retired hw_event or not.
> >  	 */
> > -	cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full);
> > +	cpuid(0xA, &eax.full, &ebx.full, &fixed_mask, &edx.full);
> >  	if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
> >  		return -ENODEV;
> 
> But now the data type names and the cpuid calls are no longer related.

oh, right, missed that. How about we change those too e.g union cpuid_0xa_eax?
diff mbox series

Patch

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 14f0a746257d..5af084198c8f 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -5903,7 +5903,7 @@  __init int intel_pmu_init(void)
 	 * Check whether the Architectural PerfMon supports
 	 * Branch Misses Retired hw_event or not.
 	 */
-	cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full);
+	cpuid(0xA, &eax.full, &ebx.full, &fixed_mask, &edx.full);
 	if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
 		return -ENODEV;
 
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index c3b0d15a9841..27048b7f23a0 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -1506,7 +1506,7 @@  void __init intel_pmu_arch_lbr_init(void)
 	u64 lbr_nr;
 
 	/* Arch LBR Capabilities */
-	cpuid(28, &eax.full, &ebx.full, &ecx.full, &unused_edx);
+	cpuid(0x1C, &eax.full, &ebx.full, &ecx.full, &unused_edx);
 
 	lbr_nr = fls(eax.split.lbr_depth_mask) * 8;
 	if (!lbr_nr)
diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c
index 42a55794004a..da3c5d748365 100644
--- a/arch/x86/events/intel/pt.c
+++ b/arch/x86/events/intel/pt.c
@@ -235,7 +235,7 @@  static int __init pt_pmu_hw_init(void)
 	}
 
 	for (i = 0; i < PT_CPUID_LEAVES; i++) {
-		cpuid_count(20, i,
+		cpuid_count(0x14, i,
 			    &pt_pmu.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM],
 			    &pt_pmu.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM],
 			    &pt_pmu.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM],